FlintyLemming/PLFM_RADAR
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fix(scripts): make Vivado TCL scripts portable and update RTL file lists

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- Replace hardcoded /home/jason-stone/ paths with [info script]-relative
  path resolution in all 9 scripts (build17-21, insert_ila_probes,
  program_fpga, ila_capture, run_cdc_and_netlist)
- Point constraint references at tracked XDC files instead of
  untracked synth_only.xdc
- Remove six phantom RTL entries (chirp_lut_init.v, fft_1024_forward.v,
  fft_1024_inverse.v, level_shifter_interface.v, lvds_to_cmos_400m.v,
  usb_packet_analyzer.v)
- Add six existing modules to file lists (rx_gain_control.v,
  mti_canceller.v, cfar_ca.v, fpga_self_test.v, xfft_16.v,
  adc_clk_mmcm.v)

Closes #38
This commit is contained in:
Serhii
2026-04-06 22:53:42 +03:00
parent 22758fa370
commit 48b3847256
9 changed files with 84 additions and 72 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/scripts/build17_production.tcl
+13 -12
View File
@@ -26,8 +26,8 @@
# #
# Usage: # Usage:
# vivado -mode batch -source build17_production.tcl \ # vivado -mode batch -source build17_production.tcl \
# -log ~/PLFM_RADAR_work/vivado_project/build17.log \ # -log build/build17.log \
# -journal ~/PLFM_RADAR_work/vivado_project/build17.jou # -journal build/build17.jou
# #
# Author: auto-generated for Jason Stone # Author: auto-generated for Jason Stone
# Date: 2026-03-19 # Date: 2026-03-19
@@ -38,8 +38,10 @@
# ============================================================================== # ==============================================================================
set project_name "aeris10_radar" set project_name "aeris10_radar"
set project_dir "/home/jason-stone/PLFM_RADAR_work/vivado_project" set script_dir [file dirname [file normalize [info script]]]
set rtl_dir "/home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA" set project_root [file normalize [file join $script_dir ".."]]
set project_dir [file join $project_root "build"]
set rtl_dir $project_root
set top_module "radar_system_top" set top_module "radar_system_top"
set fpga_part "xc7a200tfbg484-2" set fpga_part "xc7a200tfbg484-2"
set report_dir "${project_dir}/reports_build17" set report_dir "${project_dir}/reports_build17"
@@ -74,7 +76,6 @@ set_property target_language Verilog [current_project]
set rtl_files [list \ set rtl_files [list \
"${rtl_dir}/ad9484_interface_400m.v" \ "${rtl_dir}/ad9484_interface_400m.v" \
"${rtl_dir}/cdc_modules.v" \ "${rtl_dir}/cdc_modules.v" \
"${rtl_dir}/chirp_lut_init.v" \
"${rtl_dir}/chirp_memory_loader_param.v" \ "${rtl_dir}/chirp_memory_loader_param.v" \
"${rtl_dir}/cic_decimator_4x_enhanced.v" \ "${rtl_dir}/cic_decimator_4x_enhanced.v" \
"${rtl_dir}/dac_interface_single.v" \ "${rtl_dir}/dac_interface_single.v" \
@@ -82,13 +83,9 @@ set rtl_files [list \
"${rtl_dir}/ddc_input_interface.v" \ "${rtl_dir}/ddc_input_interface.v" \
"${rtl_dir}/doppler_processor.v" \ "${rtl_dir}/doppler_processor.v" \
"${rtl_dir}/edge_detector.v" \ "${rtl_dir}/edge_detector.v" \
"${rtl_dir}/fft_1024_forward.v" \
"${rtl_dir}/fft_1024_inverse.v" \
"${rtl_dir}/fir_lowpass.v" \ "${rtl_dir}/fir_lowpass.v" \
"${rtl_dir}/frequency_matched_filter.v" \ "${rtl_dir}/frequency_matched_filter.v" \
"${rtl_dir}/latency_buffer.v" \ "${rtl_dir}/latency_buffer.v" \
"${rtl_dir}/level_shifter_interface.v" \
"${rtl_dir}/lvds_to_cmos_400m.v" \
"${rtl_dir}/matched_filter_multi_segment.v" \ "${rtl_dir}/matched_filter_multi_segment.v" \
"${rtl_dir}/matched_filter_processing_chain.v" \ "${rtl_dir}/matched_filter_processing_chain.v" \
"${rtl_dir}/nco_400m_enhanced.v" \ "${rtl_dir}/nco_400m_enhanced.v" \
@@ -98,10 +95,14 @@ set rtl_files [list \
"${rtl_dir}/radar_system_top.v" \ "${rtl_dir}/radar_system_top.v" \
"${rtl_dir}/radar_transmitter.v" \ "${rtl_dir}/radar_transmitter.v" \
"${rtl_dir}/range_bin_decimator.v" \ "${rtl_dir}/range_bin_decimator.v" \
"${rtl_dir}/rx_gain_control.v" \
"${rtl_dir}/mti_canceller.v" \
"${rtl_dir}/cfar_ca.v" \
"${rtl_dir}/fpga_self_test.v" \
"${rtl_dir}/usb_data_interface.v" \ "${rtl_dir}/usb_data_interface.v" \
"${rtl_dir}/usb_packet_analyzer.v" \ "${rtl_dir}/xfft_16.v" \
"${rtl_dir}/xfft_32.v" \
"${rtl_dir}/fft_engine.v" \ "${rtl_dir}/fft_engine.v" \
"${rtl_dir}/adc_clk_mmcm.v" \
] ]
set file_count 0 set file_count 0
@@ -123,7 +124,7 @@ foreach f $mem_files {
} }
# Add constraints # Add constraints
add_files -fileset constrs_1 -norecurse "${project_dir}/synth_only.xdc" add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
set_property top $top_module [current_fileset] set_property top $top_module [current_fileset]
set_property verilog_define {FFT_XPM_BRAM} [current_fileset] set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
9_Firmware/9_2_FPGA/scripts/build18_production.tcl
+13 -12
View File
@@ -32,8 +32,8 @@
# #
# Usage: # Usage:
# vivado -mode batch -source build18_production.tcl \ # vivado -mode batch -source build18_production.tcl \
# -log ~/PLFM_RADAR_work/vivado_project/build18.log \ # -log build/build18.log \
# -journal ~/PLFM_RADAR_work/vivado_project/build18.jou # -journal build/build18.jou
# #
# Author: auto-generated for Jason Stone # Author: auto-generated for Jason Stone
# Date: 2026-03-19 # Date: 2026-03-19
@@ -44,8 +44,10 @@
# ============================================================================== # ==============================================================================
set project_name "aeris10_radar" set project_name "aeris10_radar"
set project_dir "/home/jason-stone/PLFM_RADAR_work/vivado_project" set script_dir [file dirname [file normalize [info script]]]
set rtl_dir "/home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA" set project_root [file normalize [file join $script_dir ".."]]
set project_dir [file join $project_root "build"]
set rtl_dir $project_root
set top_module "radar_system_top" set top_module "radar_system_top"
set fpga_part "xc7a200tfbg484-2" set fpga_part "xc7a200tfbg484-2"
set report_dir "${project_dir}/reports_build18" set report_dir "${project_dir}/reports_build18"
@@ -80,7 +82,6 @@ set_property target_language Verilog [current_project]
set rtl_files [list \ set rtl_files [list \
"${rtl_dir}/ad9484_interface_400m.v" \ "${rtl_dir}/ad9484_interface_400m.v" \
"${rtl_dir}/cdc_modules.v" \ "${rtl_dir}/cdc_modules.v" \
"${rtl_dir}/chirp_lut_init.v" \
"${rtl_dir}/chirp_memory_loader_param.v" \ "${rtl_dir}/chirp_memory_loader_param.v" \
"${rtl_dir}/cic_decimator_4x_enhanced.v" \ "${rtl_dir}/cic_decimator_4x_enhanced.v" \
"${rtl_dir}/dac_interface_single.v" \ "${rtl_dir}/dac_interface_single.v" \
@@ -88,13 +89,9 @@ set rtl_files [list \
"${rtl_dir}/ddc_input_interface.v" \ "${rtl_dir}/ddc_input_interface.v" \
"${rtl_dir}/doppler_processor.v" \ "${rtl_dir}/doppler_processor.v" \
"${rtl_dir}/edge_detector.v" \ "${rtl_dir}/edge_detector.v" \
"${rtl_dir}/fft_1024_forward.v" \
"${rtl_dir}/fft_1024_inverse.v" \
"${rtl_dir}/fir_lowpass.v" \ "${rtl_dir}/fir_lowpass.v" \
"${rtl_dir}/frequency_matched_filter.v" \ "${rtl_dir}/frequency_matched_filter.v" \
"${rtl_dir}/latency_buffer.v" \ "${rtl_dir}/latency_buffer.v" \
"${rtl_dir}/level_shifter_interface.v" \
"${rtl_dir}/lvds_to_cmos_400m.v" \
"${rtl_dir}/matched_filter_multi_segment.v" \ "${rtl_dir}/matched_filter_multi_segment.v" \
"${rtl_dir}/matched_filter_processing_chain.v" \ "${rtl_dir}/matched_filter_processing_chain.v" \
"${rtl_dir}/nco_400m_enhanced.v" \ "${rtl_dir}/nco_400m_enhanced.v" \
@@ -104,10 +101,14 @@ set rtl_files [list \
"${rtl_dir}/radar_system_top.v" \ "${rtl_dir}/radar_system_top.v" \
"${rtl_dir}/radar_transmitter.v" \ "${rtl_dir}/radar_transmitter.v" \
"${rtl_dir}/range_bin_decimator.v" \ "${rtl_dir}/range_bin_decimator.v" \
"${rtl_dir}/rx_gain_control.v" \
"${rtl_dir}/mti_canceller.v" \
"${rtl_dir}/cfar_ca.v" \
"${rtl_dir}/fpga_self_test.v" \
"${rtl_dir}/usb_data_interface.v" \ "${rtl_dir}/usb_data_interface.v" \
"${rtl_dir}/usb_packet_analyzer.v" \ "${rtl_dir}/xfft_16.v" \
"${rtl_dir}/xfft_32.v" \
"${rtl_dir}/fft_engine.v" \ "${rtl_dir}/fft_engine.v" \
"${rtl_dir}/adc_clk_mmcm.v" \
] ]
set file_count 0 set file_count 0
@@ -129,7 +130,7 @@ foreach f $mem_files {
} }
# Add constraints # Add constraints
add_files -fileset constrs_1 -norecurse "${project_dir}/synth_only.xdc" add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
set_property top $top_module [current_fileset] set_property top $top_module [current_fileset]
set_property verilog_define {FFT_XPM_BRAM} [current_fileset] set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
9_Firmware/9_2_FPGA/scripts/build19_mmcm.tcl
+13 -13
View File
@@ -21,8 +21,8 @@
# #
# Usage: # Usage:
# vivado -mode batch -source build19_mmcm.tcl \ # vivado -mode batch -source build19_mmcm.tcl \
# -log ~/PLFM_RADAR_work/vivado_project/build19.log \ # -log build/build19.log \
# -journal ~/PLFM_RADAR_work/vivado_project/build19.jou # -journal build/build19.jou
# #
# Author: auto-generated for Jason Stone # Author: auto-generated for Jason Stone
# Date: 2026-03-19 # Date: 2026-03-19
@@ -33,8 +33,10 @@
# ============================================================================== # ==============================================================================
set project_name "aeris10_radar" set project_name "aeris10_radar"
set project_dir "/home/jason-stone/PLFM_RADAR_work/vivado_project" set script_dir [file dirname [file normalize [info script]]]
set rtl_dir "/home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA" set project_root [file normalize [file join $script_dir ".."]]
set project_dir [file join $project_root "build"]
set rtl_dir $project_root
set top_module "radar_system_top" set top_module "radar_system_top"
set fpga_part "xc7a200tfbg484-2" set fpga_part "xc7a200tfbg484-2"
set report_dir "${project_dir}/reports_build19" set report_dir "${project_dir}/reports_build19"
@@ -71,7 +73,6 @@ set rtl_files [list \
"${rtl_dir}/adc_clk_mmcm.v" \ "${rtl_dir}/adc_clk_mmcm.v" \
"${rtl_dir}/ad9484_interface_400m.v" \ "${rtl_dir}/ad9484_interface_400m.v" \
"${rtl_dir}/cdc_modules.v" \ "${rtl_dir}/cdc_modules.v" \
"${rtl_dir}/chirp_lut_init.v" \
"${rtl_dir}/chirp_memory_loader_param.v" \ "${rtl_dir}/chirp_memory_loader_param.v" \
"${rtl_dir}/cic_decimator_4x_enhanced.v" \ "${rtl_dir}/cic_decimator_4x_enhanced.v" \
"${rtl_dir}/dac_interface_single.v" \ "${rtl_dir}/dac_interface_single.v" \
@@ -79,13 +80,9 @@ set rtl_files [list \
"${rtl_dir}/ddc_input_interface.v" \ "${rtl_dir}/ddc_input_interface.v" \
"${rtl_dir}/doppler_processor.v" \ "${rtl_dir}/doppler_processor.v" \
"${rtl_dir}/edge_detector.v" \ "${rtl_dir}/edge_detector.v" \
"${rtl_dir}/fft_1024_forward.v" \
"${rtl_dir}/fft_1024_inverse.v" \
"${rtl_dir}/fir_lowpass.v" \ "${rtl_dir}/fir_lowpass.v" \
"${rtl_dir}/frequency_matched_filter.v" \ "${rtl_dir}/frequency_matched_filter.v" \
"${rtl_dir}/latency_buffer.v" \ "${rtl_dir}/latency_buffer.v" \
"${rtl_dir}/level_shifter_interface.v" \
"${rtl_dir}/lvds_to_cmos_400m.v" \
"${rtl_dir}/matched_filter_multi_segment.v" \ "${rtl_dir}/matched_filter_multi_segment.v" \
"${rtl_dir}/matched_filter_processing_chain.v" \ "${rtl_dir}/matched_filter_processing_chain.v" \
"${rtl_dir}/nco_400m_enhanced.v" \ "${rtl_dir}/nco_400m_enhanced.v" \
@@ -95,9 +92,12 @@ set rtl_files [list \
"${rtl_dir}/radar_system_top.v" \ "${rtl_dir}/radar_system_top.v" \
"${rtl_dir}/radar_transmitter.v" \ "${rtl_dir}/radar_transmitter.v" \
"${rtl_dir}/range_bin_decimator.v" \ "${rtl_dir}/range_bin_decimator.v" \
"${rtl_dir}/rx_gain_control.v" \
"${rtl_dir}/mti_canceller.v" \
"${rtl_dir}/cfar_ca.v" \
"${rtl_dir}/fpga_self_test.v" \
"${rtl_dir}/usb_data_interface.v" \ "${rtl_dir}/usb_data_interface.v" \
"${rtl_dir}/usb_packet_analyzer.v" \ "${rtl_dir}/xfft_16.v" \
"${rtl_dir}/xfft_32.v" \
"${rtl_dir}/fft_engine.v" \ "${rtl_dir}/fft_engine.v" \
] ]
@@ -120,8 +120,8 @@ foreach f $mem_files {
} }
# Add constraints — main production XDC + MMCM supplementary XDC # Add constraints — main production XDC + MMCM supplementary XDC
add_files -fileset constrs_1 -norecurse "${project_dir}/synth_only.xdc" add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
add_files -fileset constrs_1 -norecurse "${rtl_dir}/constraints/adc_clk_mmcm.xdc" add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "adc_clk_mmcm.xdc"]
set_property top $top_module [current_fileset] set_property top $top_module [current_fileset]
set_property verilog_define {FFT_XPM_BRAM} [current_fileset] set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
9_Firmware/9_2_FPGA/scripts/build20_mmcm_creg.tcl
+13 -13
View File
@@ -26,8 +26,8 @@
# #
# Usage: # Usage:
# vivado -mode batch -source build20_mmcm_creg.tcl \ # vivado -mode batch -source build20_mmcm_creg.tcl \
# -log ~/PLFM_RADAR_work/vivado_project/build20.log \ # -log build/build20.log \
# -journal ~/PLFM_RADAR_work/vivado_project/build20.jou # -journal build/build20.jou
# #
# Author: auto-generated for Jason Stone # Author: auto-generated for Jason Stone
# Date: 2026-03-19 # Date: 2026-03-19
@@ -38,8 +38,10 @@
# ============================================================================== # ==============================================================================
set project_name "aeris10_radar" set project_name "aeris10_radar"
set project_dir "/home/jason-stone/PLFM_RADAR_work/vivado_project" set script_dir [file dirname [file normalize [info script]]]
set rtl_dir "/home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA" set project_root [file normalize [file join $script_dir ".."]]
set project_dir [file join $project_root "build"]
set rtl_dir $project_root
set top_module "radar_system_top" set top_module "radar_system_top"
set fpga_part "xc7a200tfbg484-2" set fpga_part "xc7a200tfbg484-2"
set report_dir "${project_dir}/reports_build20" set report_dir "${project_dir}/reports_build20"
@@ -75,7 +77,6 @@ set rtl_files [list \
"${rtl_dir}/adc_clk_mmcm.v" \ "${rtl_dir}/adc_clk_mmcm.v" \
"${rtl_dir}/ad9484_interface_400m.v" \ "${rtl_dir}/ad9484_interface_400m.v" \
"${rtl_dir}/cdc_modules.v" \ "${rtl_dir}/cdc_modules.v" \
"${rtl_dir}/chirp_lut_init.v" \
"${rtl_dir}/chirp_memory_loader_param.v" \ "${rtl_dir}/chirp_memory_loader_param.v" \
"${rtl_dir}/cic_decimator_4x_enhanced.v" \ "${rtl_dir}/cic_decimator_4x_enhanced.v" \
"${rtl_dir}/dac_interface_single.v" \ "${rtl_dir}/dac_interface_single.v" \
@@ -83,13 +84,9 @@ set rtl_files [list \
"${rtl_dir}/ddc_input_interface.v" \ "${rtl_dir}/ddc_input_interface.v" \
"${rtl_dir}/doppler_processor.v" \ "${rtl_dir}/doppler_processor.v" \
"${rtl_dir}/edge_detector.v" \ "${rtl_dir}/edge_detector.v" \
"${rtl_dir}/fft_1024_forward.v" \
"${rtl_dir}/fft_1024_inverse.v" \
"${rtl_dir}/fir_lowpass.v" \ "${rtl_dir}/fir_lowpass.v" \
"${rtl_dir}/frequency_matched_filter.v" \ "${rtl_dir}/frequency_matched_filter.v" \
"${rtl_dir}/latency_buffer.v" \ "${rtl_dir}/latency_buffer.v" \
"${rtl_dir}/level_shifter_interface.v" \
"${rtl_dir}/lvds_to_cmos_400m.v" \
"${rtl_dir}/matched_filter_multi_segment.v" \ "${rtl_dir}/matched_filter_multi_segment.v" \
"${rtl_dir}/matched_filter_processing_chain.v" \ "${rtl_dir}/matched_filter_processing_chain.v" \
"${rtl_dir}/nco_400m_enhanced.v" \ "${rtl_dir}/nco_400m_enhanced.v" \
@@ -99,9 +96,12 @@ set rtl_files [list \
"${rtl_dir}/radar_system_top.v" \ "${rtl_dir}/radar_system_top.v" \
"${rtl_dir}/radar_transmitter.v" \ "${rtl_dir}/radar_transmitter.v" \
"${rtl_dir}/range_bin_decimator.v" \ "${rtl_dir}/range_bin_decimator.v" \
"${rtl_dir}/rx_gain_control.v" \
"${rtl_dir}/mti_canceller.v" \
"${rtl_dir}/cfar_ca.v" \
"${rtl_dir}/fpga_self_test.v" \
"${rtl_dir}/usb_data_interface.v" \ "${rtl_dir}/usb_data_interface.v" \
"${rtl_dir}/usb_packet_analyzer.v" \ "${rtl_dir}/xfft_16.v" \
"${rtl_dir}/xfft_32.v" \
"${rtl_dir}/fft_engine.v" \ "${rtl_dir}/fft_engine.v" \
] ]
@@ -124,8 +124,8 @@ foreach f $mem_files {
} }
# Add constraints — main production XDC + MMCM supplementary XDC (FIXED) # Add constraints — main production XDC + MMCM supplementary XDC (FIXED)
add_files -fileset constrs_1 -norecurse "${project_dir}/synth_only.xdc" add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
add_files -fileset constrs_1 -norecurse "${rtl_dir}/constraints/adc_clk_mmcm.xdc" add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "adc_clk_mmcm.xdc"]
set_property top $top_module [current_fileset] set_property top $top_module [current_fileset]
set_property verilog_define {FFT_XPM_BRAM} [current_fileset] set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
9_Firmware/9_2_FPGA/scripts/build21_fft_e2e.tcl
+13 -13
View File
@@ -32,8 +32,8 @@
# #
# Usage: # Usage:
# vivado -mode batch -source build21_fft_e2e.tcl \ # vivado -mode batch -source build21_fft_e2e.tcl \
# -log ~/PLFM_RADAR_work/vivado_project/build21.log \ # -log build/build21.log \
# -journal ~/PLFM_RADAR_work/vivado_project/build21.jou # -journal build/build21.jou
# #
# Author: auto-generated for Jason Stone # Author: auto-generated for Jason Stone
# Date: 2026-03-20 # Date: 2026-03-20
@@ -44,8 +44,10 @@
# ============================================================================== # ==============================================================================
set project_name "aeris10_radar" set project_name "aeris10_radar"
set project_dir "/home/jason-stone/PLFM_RADAR_work/vivado_project" set script_dir [file dirname [file normalize [info script]]]
set rtl_dir "/home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA" set project_root [file normalize [file join $script_dir ".."]]
set project_dir [file join $project_root "build"]
set rtl_dir $project_root
set top_module "radar_system_top" set top_module "radar_system_top"
set fpga_part "xc7a200tfbg484-2" set fpga_part "xc7a200tfbg484-2"
set report_dir "${project_dir}/reports_build21" set report_dir "${project_dir}/reports_build21"
@@ -81,7 +83,6 @@ set rtl_files [list \
"${rtl_dir}/adc_clk_mmcm.v" \ "${rtl_dir}/adc_clk_mmcm.v" \
"${rtl_dir}/ad9484_interface_400m.v" \ "${rtl_dir}/ad9484_interface_400m.v" \
"${rtl_dir}/cdc_modules.v" \ "${rtl_dir}/cdc_modules.v" \
"${rtl_dir}/chirp_lut_init.v" \
"${rtl_dir}/chirp_memory_loader_param.v" \ "${rtl_dir}/chirp_memory_loader_param.v" \
"${rtl_dir}/cic_decimator_4x_enhanced.v" \ "${rtl_dir}/cic_decimator_4x_enhanced.v" \
"${rtl_dir}/dac_interface_single.v" \ "${rtl_dir}/dac_interface_single.v" \
@@ -89,13 +90,9 @@ set rtl_files [list \
"${rtl_dir}/ddc_input_interface.v" \ "${rtl_dir}/ddc_input_interface.v" \
"${rtl_dir}/doppler_processor.v" \ "${rtl_dir}/doppler_processor.v" \
"${rtl_dir}/edge_detector.v" \ "${rtl_dir}/edge_detector.v" \
"${rtl_dir}/fft_1024_forward.v" \
"${rtl_dir}/fft_1024_inverse.v" \
"${rtl_dir}/fir_lowpass.v" \ "${rtl_dir}/fir_lowpass.v" \
"${rtl_dir}/frequency_matched_filter.v" \ "${rtl_dir}/frequency_matched_filter.v" \
"${rtl_dir}/latency_buffer.v" \ "${rtl_dir}/latency_buffer.v" \
"${rtl_dir}/level_shifter_interface.v" \
"${rtl_dir}/lvds_to_cmos_400m.v" \
"${rtl_dir}/matched_filter_multi_segment.v" \ "${rtl_dir}/matched_filter_multi_segment.v" \
"${rtl_dir}/matched_filter_processing_chain.v" \ "${rtl_dir}/matched_filter_processing_chain.v" \
"${rtl_dir}/nco_400m_enhanced.v" \ "${rtl_dir}/nco_400m_enhanced.v" \
@@ -105,9 +102,12 @@ set rtl_files [list \
"${rtl_dir}/radar_system_top.v" \ "${rtl_dir}/radar_system_top.v" \
"${rtl_dir}/radar_transmitter.v" \ "${rtl_dir}/radar_transmitter.v" \
"${rtl_dir}/range_bin_decimator.v" \ "${rtl_dir}/range_bin_decimator.v" \
"${rtl_dir}/rx_gain_control.v" \
"${rtl_dir}/mti_canceller.v" \
"${rtl_dir}/cfar_ca.v" \
"${rtl_dir}/fpga_self_test.v" \
"${rtl_dir}/usb_data_interface.v" \ "${rtl_dir}/usb_data_interface.v" \
"${rtl_dir}/usb_packet_analyzer.v" \ "${rtl_dir}/xfft_16.v" \
"${rtl_dir}/xfft_32.v" \
"${rtl_dir}/fft_engine.v" \ "${rtl_dir}/fft_engine.v" \
] ]
@@ -130,8 +130,8 @@ foreach f $mem_files {
} }
# Add constraints — main production XDC + MMCM supplementary XDC (FIXED) # Add constraints — main production XDC + MMCM supplementary XDC (FIXED)
add_files -fileset constrs_1 -norecurse "${project_dir}/synth_only.xdc" add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
add_files -fileset constrs_1 -norecurse "${rtl_dir}/constraints/adc_clk_mmcm.xdc" add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "adc_clk_mmcm.xdc"]
set_property top $top_module [current_fileset] set_property top $top_module [current_fileset]
set_property verilog_define {FFT_XPM_BRAM} [current_fileset] set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
9_Firmware/9_2_FPGA/scripts/ila_capture.tcl
+6 -3
View File
@@ -34,7 +34,10 @@
set default_server "localhost" set default_server "localhost"
set default_port 3121 set default_port 3121
set default_ltx "/home/jason-stone/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top.ltx" set script_dir [file dirname [file normalize [info script]]]
set project_root [file normalize [file join $script_dir ".."]]
set default_ltx [file join $project_root "build" "aeris10_radar.runs" "impl_ila" "radar_system_top.ltx"]
set default_output_base [file join $project_root "build" "captures"]
set default_depth 4096 set default_depth 4096
set default_timeout 30 set default_timeout 30
@@ -108,7 +111,7 @@ proc log_kv {key value} {
proc parse_args {} { proc parse_args {} {
global argc argv global argc argv
global default_server default_port default_ltx default_depth default_timeout global default_server default_port default_ltx default_output_base default_depth default_timeout
global hw_server_host hw_server_port probes_path capture_depth trigger_timeout global hw_server_host hw_server_port probes_path capture_depth trigger_timeout
global capture_scenario use_immediate output_dir global capture_scenario use_immediate output_dir
@@ -185,7 +188,7 @@ proc parse_args {} {
# Auto-generate timestamped output directory if not specified # Auto-generate timestamped output directory if not specified
if {$output_dir eq ""} { if {$output_dir eq ""} {
set timestamp [clock format [clock seconds] -format {%Y%m%d_%H%M%S}] set timestamp [clock format [clock seconds] -format {%Y%m%d_%H%M%S}]
set output_dir "/home/jason-stone/PLFM_RADAR_work/vivado_project/captures/ila_${capture_scenario}_${timestamp}" set output_dir [file join $default_output_base "ila_${capture_scenario}_${timestamp}"]
} }
} }
9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl
+4 -2
View File
@@ -32,9 +32,11 @@
# 0. Configuration — all paths and parameters in one place # 0. Configuration — all paths and parameters in one place
# ============================================================================== # ==============================================================================
set project_base "/home/jason-stone/PLFM_RADAR_work/vivado_project" set script_dir [file dirname [file normalize [info script]]]
set project_root [file normalize [file join $script_dir ".."]]
set project_base [file join $project_root "build"]
set synth_dcp "${project_base}/aeris10_radar.runs/synth_1/radar_system_top.dcp" set synth_dcp "${project_base}/aeris10_radar.runs/synth_1/radar_system_top.dcp"
set synth_xdc "${project_base}/synth_only.xdc" set synth_xdc [file join $project_root "constraints" "xc7a200t_fbg484.xdc"]
set output_dir "${project_base}/aeris10_radar.runs/impl_ila" set output_dir "${project_base}/aeris10_radar.runs/impl_ila"
set top_module "radar_system_top" set top_module "radar_system_top"
set part "xc7a200tfbg484-2" set part "xc7a200tfbg484-2"
9_Firmware/9_2_FPGA/scripts/program_fpga.tcl
+4 -2
View File
@@ -25,8 +25,10 @@
set default_server "localhost" set default_server "localhost"
set default_port 3121 set default_port 3121
set default_bit "/home/jason-stone/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top.bit" set script_dir [file dirname [file normalize [info script]]]
set default_ltx "/home/jason-stone/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top.ltx" set project_root [file normalize [file join $script_dir ".."]]
set default_bit [file join $project_root "build" "bitstream" "radar_system_top_build21.bit"]
set default_ltx [file join $project_root "build" "aeris10_radar.runs" "impl_ila" "radar_system_top.ltx"]
set expected_part "xc7a200t" set expected_part "xc7a200t"
set expected_pkg "fbg484" set expected_pkg "fbg484"
9_Firmware/9_2_FPGA/scripts/run_cdc_and_netlist.tcl
+4 -1
View File
@@ -5,8 +5,11 @@
# #
# Usage: vivado -mode batch -source run_cdc_and_netlist.tcl # Usage: vivado -mode batch -source run_cdc_and_netlist.tcl
set project_dir "/home/jason-stone/PLFM_RADAR_work/vivado_project" set script_dir [file dirname [file normalize [info script]]]
set project_root [file normalize [file join $script_dir ".."]]
set project_dir [file join $project_root "build"]
set report_dir "${project_dir}/reports_impl" set report_dir "${project_dir}/reports_impl"
file mkdir $report_dir
# Open the routed checkpoint # Open the routed checkpoint
open_checkpoint ${project_dir}/aeris10_radar.runs/impl_1/radar_system_top_routed.dcp open_checkpoint ${project_dir}/aeris10_radar.runs/impl_1/radar_system_top_routed.dcp