CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner
- cic_decimator_4x_enhanced.v: Add integrator_sampled_comb and data_valid_comb_pipe pipeline stages between integrator sampling and comb computation to break the critical path (matches remote 40cda0f) - radar_system_top.v: Wrap 3 BUFG instances in ifdef SIMULATION guard with pass-through assigns for iverilog compatibility - radar_system_tb.v: Convert generate_radar_echo function to task and move sin_lut declaration before task (iverilog declaration-order fix), add modular index clamping to prevent LUT out-of-bounds - run_regression.sh: Automated regression runner for all 18 FPGA testbenches with --quick mode. Results: 17 pass, 1 pre-existing fail - .gitignore: Exclude *.vvp, *.vcd simulation artifacts
This commit is contained in:
Jason
Executable
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#!/bin/bash
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# ===========================================================================
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# FPGA Regression Test Runner for AERIS-10 Radar
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# Runs all verified iverilog testbenches and reports pass/fail summary.
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#
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# Usage: ./run_regression.sh [--quick]
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# --quick Skip long-running integration tests (receiver golden, system TB)
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#
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# Exit code: 0 if all tests pass, 1 if any fail
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# ===========================================================================
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set -euo pipefail
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SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)"
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cd "$SCRIPT_DIR"
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QUICK=0
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if [[ "${1:-}" == "--quick" ]]; then
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QUICK=1
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fi
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PASS=0
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FAIL=0
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SKIP=0
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ERRORS=""
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# Colors (if terminal supports it)
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RED='\033[0;31m'
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GREEN='\033[0;32m'
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YELLOW='\033[0;33m'
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NC='\033[0m' # No Color
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# ---------------------------------------------------------------------------
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# Helper: compile and run a single testbench
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# run_test <name> <vvp_path> <iverilog_args...>
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# ---------------------------------------------------------------------------
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run_test() {
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local name="$1"
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local vvp="$2"
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shift 2
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local args=("$@")
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printf " %-45s " "$name"
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# Compile
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if ! iverilog -g2001 -DSIMULATION -o "$vvp" "${args[@]}" 2>/tmp/iverilog_err_$$; then
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echo -e "${RED}COMPILE FAIL${NC}"
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ERRORS="$ERRORS\n $name: compile error ($(head -1 /tmp/iverilog_err_$$))"
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FAIL=$((FAIL + 1))
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return
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fi
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# Run
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local output
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output=$(timeout 120 vvp "$vvp" 2>&1) || true
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# Count PASS/FAIL in output (testbenches use explicit [PASS]/[FAIL] markers)
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local test_pass test_fail
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test_pass=$(echo "$output" | grep -ci '\bPASS\b' || true)
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test_fail=$(echo "$output" | grep -ci '\bFAIL\b' || true)
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if [[ "$test_fail" -gt 0 ]]; then
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echo -e "${RED}FAIL${NC} (pass=$test_pass, fail=$test_fail)"
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ERRORS="$ERRORS\n $name: $test_fail failure(s)"
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FAIL=$((FAIL + 1))
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elif [[ "$test_pass" -gt 0 ]]; then
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echo -e "${GREEN}PASS${NC} ($test_pass checks)"
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PASS=$((PASS + 1))
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else
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# No PASS/FAIL markers — check for clean completion
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if echo "$output" | grep -qi 'finish\|complete\|done'; then
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echo -e "${GREEN}PASS${NC} (completed)"
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PASS=$((PASS + 1))
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else
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echo -e "${YELLOW}UNKNOWN${NC} (no PASS/FAIL markers)"
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ERRORS="$ERRORS\n $name: no pass/fail markers in output"
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FAIL=$((FAIL + 1))
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fi
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fi
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rm -f "$vvp"
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}
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# ===========================================================================
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echo "============================================"
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echo " AERIS-10 FPGA Regression Test Suite"
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echo "============================================"
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echo ""
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echo "Date: $(date)"
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echo "iverilog: $(iverilog -V 2>&1 | head -1)"
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echo ""
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# ===========================================================================
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# UNIT TESTS — Changed Modules (HIGH PRIORITY)
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# ===========================================================================
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echo "--- HIGH PRIORITY: Changed Modules ---"
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run_test "CIC Decimator" \
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tb/tb_cic_reg.vvp \
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tb/tb_cic_decimator.v cic_decimator_4x_enhanced.v
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run_test "Chirp Controller (BRAM)" \
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tb/tb_chirp_reg.vvp \
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tb/tb_chirp_controller.v plfm_chirp_controller.v
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run_test "Chirp Contract" \
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tb/tb_chirp_ctr_reg.vvp \
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tb/tb_chirp_contract.v plfm_chirp_controller.v
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run_test "Doppler Processor (DSP48)" \
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tb/tb_doppler_reg.vvp \
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tb/tb_doppler_cosim.v doppler_processor.v xfft_32.v fft_engine.v
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echo ""
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# ===========================================================================
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# INTEGRATION TESTS
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# ===========================================================================
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echo "--- INTEGRATION TESTS ---"
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run_test "DDC Chain (NCO→CIC→FIR)" \
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tb/tb_ddc_reg.vvp \
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tb/tb_ddc_cosim.v ddc_400m.v nco_400m_enhanced.v \
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cic_decimator_4x_enhanced.v fir_lowpass.v cdc_modules.v
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if [[ "$QUICK" -eq 0 ]]; then
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# Golden generate
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run_test "Receiver (golden generate)" \
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tb/tb_rx_golden_reg.vvp \
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-DGOLDEN_GENERATE \
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tb/tb_radar_receiver_final.v radar_receiver_final.v \
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radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
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ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
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cdc_modules.v fir_lowpass.v ddc_input_interface.v \
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chirp_memory_loader_param.v latency_buffer.v \
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matched_filter_multi_segment.v matched_filter_processing_chain.v \
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range_bin_decimator.v doppler_processor.v xfft_32.v fft_engine.v
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# Golden compare
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run_test "Receiver (golden compare)" \
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tb/tb_rx_compare_reg.vvp \
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tb/tb_radar_receiver_final.v radar_receiver_final.v \
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radar_mode_controller.v tb/ad9484_interface_400m_stub.v \
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ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
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cdc_modules.v fir_lowpass.v ddc_input_interface.v \
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chirp_memory_loader_param.v latency_buffer.v \
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matched_filter_multi_segment.v matched_filter_processing_chain.v \
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range_bin_decimator.v doppler_processor.v xfft_32.v fft_engine.v
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# Full system top
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run_test "System Top (radar_system_tb)" \
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tb/tb_system_reg.vvp \
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tb/radar_system_tb.v radar_system_top.v \
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radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
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radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
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ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
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cdc_modules.v fir_lowpass.v ddc_input_interface.v \
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chirp_memory_loader_param.v latency_buffer.v \
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matched_filter_multi_segment.v matched_filter_processing_chain.v \
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range_bin_decimator.v doppler_processor.v xfft_32.v fft_engine.v \
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usb_data_interface.v edge_detector.v radar_mode_controller.v
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else
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echo " (skipped receiver golden + system top — use without --quick)"
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SKIP=$((SKIP + 3))
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fi
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echo ""
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# ===========================================================================
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# UNIT TESTS — Signal Processing
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# ===========================================================================
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echo "--- UNIT TESTS: Signal Processing ---"
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run_test "FFT Engine" \
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tb/tb_fft_reg.vvp \
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tb/tb_fft_engine.v fft_engine.v
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run_test "XFFT-32 Wrapper" \
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tb/tb_xfft_reg.vvp \
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tb/tb_xfft_32.v xfft_32.v fft_engine.v
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run_test "NCO 400MHz" \
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tb/tb_nco_reg.vvp \
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tb/tb_nco_400m.v nco_400m_enhanced.v
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run_test "FIR Lowpass" \
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tb/tb_fir_reg.vvp \
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tb/tb_fir_lowpass.v fir_lowpass.v
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run_test "Matched Filter Chain" \
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tb/tb_mf_reg.vvp \
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tb/tb_matched_filter_processing_chain.v matched_filter_processing_chain.v \
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xfft_32.v fft_engine.v chirp_memory_loader_param.v
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echo ""
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# ===========================================================================
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# UNIT TESTS — Infrastructure
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# ===========================================================================
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echo "--- UNIT TESTS: Infrastructure ---"
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run_test "CDC Modules (3 variants)" \
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tb/tb_cdc_reg.vvp \
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tb/tb_cdc_modules.v cdc_modules.v
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run_test "Edge Detector" \
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tb/tb_edge_reg.vvp \
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tb/tb_edge_detector.v edge_detector.v
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run_test "USB Data Interface" \
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tb/tb_usb_reg.vvp \
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tb/tb_usb_data_interface.v usb_data_interface.v
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run_test "Range Bin Decimator" \
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tb/tb_rbd_reg.vvp \
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tb/tb_range_bin_decimator.v range_bin_decimator.v
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run_test "Radar Mode Controller" \
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tb/tb_rmc_reg.vvp \
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tb/tb_radar_mode_controller.v radar_mode_controller.v
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echo ""
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# ===========================================================================
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# SUMMARY
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# ===========================================================================
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TOTAL=$((PASS + FAIL + SKIP))
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echo "============================================"
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echo " RESULTS: $PASS passed, $FAIL failed, $SKIP skipped / $TOTAL total"
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echo "============================================"
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if [[ -n "$ERRORS" ]]; then
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echo ""
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echo "Failures:"
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echo -e "$ERRORS"
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fi
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echo ""
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# Exit with error if any failures
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if [[ "$FAIL" -gt 0 ]]; then
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exit 1
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fi
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exit 0
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