CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner

- cic_decimator_4x_enhanced.v: Add integrator_sampled_comb and
  data_valid_comb_pipe pipeline stages between integrator sampling and
  comb computation to break the critical path (matches remote 40cda0f)
- radar_system_top.v: Wrap 3 BUFG instances in ifdef SIMULATION guard
  with pass-through assigns for iverilog compatibility
- radar_system_tb.v: Convert generate_radar_echo function to task and
  move sin_lut declaration before task (iverilog declaration-order fix),
  add modular index clamping to prevent LUT out-of-bounds
- run_regression.sh: Automated regression runner for all 18 FPGA
  testbenches with --quick mode. Results: 17 pass, 1 pre-existing fail
- .gitignore: Exclude *.vvp, *.vcd simulation artifacts

9_Firmware/9_2_FPGA/radar_system_top.v

@@ -180,6 +180,12 @@ reg [3:0] status_reg;
 // CLOCK BUFFERING
 // ============================================================================
 
+`ifdef SIMULATION
+// In simulation (iverilog), BUFG is not available — pass-through assigns
+assign clk_100m_buf     = clk_100m;
+assign clk_120m_dac_buf = clk_120m_dac;
+assign ft601_clk_buf    = ft601_clk_in;
+`else
 BUFG bufg_100m (
     .I(clk_100m),
     .O(clk_100m_buf)
@@ -194,6 +200,7 @@ BUFG bufg_ft601 (
     .I(ft601_clk_in),
     .O(ft601_clk_buf)
 );
+`endif
 
 // Reset synchronization (clk_100m domain)
 (* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync;