CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner

- cic_decimator_4x_enhanced.v: Add integrator_sampled_comb and
  data_valid_comb_pipe pipeline stages between integrator sampling and
  comb computation to break the critical path (matches remote 40cda0f)
- radar_system_top.v: Wrap 3 BUFG instances in ifdef SIMULATION guard
  with pass-through assigns for iverilog compatibility
- radar_system_tb.v: Convert generate_radar_echo function to task and
  move sin_lut declaration before task (iverilog declaration-order fix),
  add modular index clamping to prevent LUT out-of-bounds
- run_regression.sh: Automated regression runner for all 18 FPGA
  testbenches with --quick mode. Results: 17 pass, 1 pre-existing fail
- .gitignore: Exclude *.vvp, *.vcd simulation artifacts

9_Firmware/9_2_FPGA/.gitignore

@@ -0,0 +1,12 @@
+# Simulation build artifacts
+*.vvp
+*.vcd
+tb/*.vvp
+tb/*.vcd
+
+# Vivado project files (managed separately)
+*.jou
+*.log
+*.str
+*.bit
+*.ltx