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fix(constraints): change adc_pwdn from LVCMOS33 to LVCMOS25 for Bank 14 compatibility

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The placer enforces a single VCCO per bank. LVDS_25 forces Bank 14
to VCCO=2.5V, which conflicts with LVCMOS33 (needs 3.3V). Changing
adc_pwdn to LVCMOS25 resolves [Place 30-372] bank incompatibility.
The AD9484 PWDN pin has CMOS-level thresholds (~0.8V), so 2.5V
output drives it correctly.
This commit is contained in:
Jason
2026-04-07 06:07:47 +03:00
parent 96856c42e0
commit 44460e7443
2 changed files with 15 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
+11 -9
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@@ -12,7 +12,7 @@
# #
# I/O Bank Voltage Summary: # I/O Bank Voltage Summary:
# Bank 0: VCCO = 3.3V (JTAG, flash CS) # Bank 0: VCCO = 3.3V (JTAG, flash CS)
# Bank 14: VCCO = 3.3V (ADC LVDS data, SPI flash, adc_pwdn) # Bank 14: VCCO = 2.5V (ADC LVDS_25 data — placer-enforced; adc_pwdn as LVCMOS25)
# Bank 15: VCCO = 3.3V (DAC, clocks, STM32 SPI 3.3V side, DIG bus, mixer) # Bank 15: VCCO = 3.3V (DAC, clocks, STM32 SPI 3.3V side, DIG bus, mixer)
# Bank 34: VCCO = 1.8V (ADAR1000 beamformer control, SPI 1.8V side) # Bank 34: VCCO = 1.8V (ADAR1000 beamformer control, SPI 1.8V side)
# Bank 35: VCCO = 3.3V (unused — no signal connections) # Bank 35: VCCO = 3.3V (unused — no signal connections)
@@ -20,11 +20,11 @@
# DRC Fix History: # DRC Fix History:
# - PLIO-9: Moved clk_120m_dac from C13 (N-type) to D13 (P-type MRCC). # - PLIO-9: Moved clk_120m_dac from C13 (N-type) to D13 (P-type MRCC).
# Clock inputs must use the P-type pin of a Multi-Region Clock-Capable pair. # Clock inputs must use the P-type pin of a Multi-Region Clock-Capable pair.
# - BIVC-1: Bank 14 has VCCO=3.3V but LVDS inputs require LVDS_25 (no LVDS_33 # - BIVC-1 / Place 30-372: Bank 14 must have a single VCCO. LVDS_25 forces
# on 7-series, LVDS requires HP banks). IBUFDS input buffers are VCCO- # VCCO=2.5V, so adc_pwdn was changed from LVCMOS33 to LVCMOS25 to match.
# independent — they work correctly with any VCCO. The BIVC-1 DRC is # IBUFDS input buffers are VCCO-independent. BIVC-1 also waived via
# conservative (aimed at OBUFDS outputs). Waived via set_property SEVERITY # set_property SEVERITY in the build script as an additional safety net.
# in the build script. adc_pwdn (LVCMOS33) coexists in the same bank. # in the build script. adc_pwdn (LVCMOS25) coexists in the same bank.
# - UCIO/NSTD: 118 unconstrained ports (FT601 unwired, status/debug outputs # - UCIO/NSTD: 118 unconstrained ports (FT601 unwired, status/debug outputs
# have no physical pins). Handled with SEVERITY demotion + default IOSTANDARD. # have no physical pins). Handled with SEVERITY demotion + default IOSTANDARD.
# ============================================================================ # ============================================================================
@@ -237,13 +237,15 @@ set_property PACKAGE_PIN R7 [get_ports {adc_d_n[7]}]
# ADC DCO Clock (LVDS) — already constrained above in CLOCK section # ADC DCO Clock (LVDS) — already constrained above in CLOCK section
# ADC Power Down — ADC_PWRD net (single-ended, Bank 14) # ADC Power Down — ADC_PWRD net (single-ended, Bank 14)
# Uses LVCMOS25 to be voltage-compatible with LVDS_25 in the same bank.
# The placer enforces a single VCCO per bank; LVDS_25 demands VCCO=2.5V.
# LVCMOS25 output drives the AD9484 PWDN pin (CMOS threshold ~0.8V) safely.
# On the physical board (VCCO=3.3V), output swings follow actual VCCO.
set_property PACKAGE_PIN T5 [get_ports {adc_pwdn}] set_property PACKAGE_PIN T5 [get_ports {adc_pwdn}]
set_property IOSTANDARD LVCMOS33 [get_ports {adc_pwdn}] set_property IOSTANDARD LVCMOS25 [get_ports {adc_pwdn}]
# LVDS I/O Standard — LVDS_25 is the only valid differential input standard # LVDS I/O Standard — LVDS_25 is the only valid differential input standard
# on 7-series HR banks. IBUFDS inputs work correctly regardless of VCCO. # on 7-series HR banks. IBUFDS inputs work correctly regardless of VCCO.
# The BIVC-1 DRC (conflict with LVCMOS33 adc_pwdn at VCCO=3.3V) is waived
# in the build script since Bank 14 has only LVDS *inputs*, no outputs.
set_property IOSTANDARD LVDS_25 [get_ports {adc_d_p[*]}] set_property IOSTANDARD LVDS_25 [get_ports {adc_d_p[*]}]
set_property IOSTANDARD LVDS_25 [get_ports {adc_d_n[*]}] set_property IOSTANDARD LVDS_25 [get_ports {adc_d_n[*]}]
9_Firmware/9_2_FPGA/scripts/build_50t_test.tcl
+4 -4
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@@ -54,10 +54,10 @@ add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "
# We still set them here for any DRC checks run in the parent context # We still set them here for any DRC checks run in the parent context
# (e.g., report_drc after open_run). # (e.g., report_drc after open_run).
# #
# BIVC-1: Bank 14 VCCO=3.3V with LVDS_25 IBUFDS inputs + LVCMOS33 adc_pwdn. # BIVC-1: Bank 14 VCCO=2.5V (enforced by LVDS_25) with LVCMOS25 adc_pwdn.
# IBUFDS inputs are VCCO-independent on 7-series (internal diff amplifier). # This should no longer fire now that adc_pwdn is LVCMOS25, but we keep
# The DRC is conservative — aimed at OBUFDS outputs where VCCO affects swing. # the waiver as a safety net in case future XDC changes re-introduce the
# Bank 14 has only LVDS *inputs*, so demoting to warning is safe. # conflict.
set_property SEVERITY {Warning} [get_drc_checks BIVC-1] set_property SEVERITY {Warning} [get_drc_checks BIVC-1]
# NSTD-1 / UCIO-1: 118 unconstrained port bits — FT601 USB 3.0 (chip unwired # NSTD-1 / UCIO-1: 118 unconstrained port bits — FT601 USB 3.0 (chip unwired