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fix(constraints): change adc_pwdn from LVCMOS33 to LVCMOS25 for Bank 14 compatibility

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The placer enforces a single VCCO per bank. LVDS_25 forces Bank 14
to VCCO=2.5V, which conflicts with LVCMOS33 (needs 3.3V). Changing
adc_pwdn to LVCMOS25 resolves [Place 30-372] bank incompatibility.
The AD9484 PWDN pin has CMOS-level thresholds (~0.8V), so 2.5V
output drives it correctly.
This commit is contained in:
Jason
2026-04-07 06:07:47 +03:00
parent 96856c42e0
commit 44460e7443
2 changed files with 15 additions and 13 deletions
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9_Firmware/9_2_FPGA/scripts/build_50t_test.tcl
+4 -4
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@@ -54,10 +54,10 @@ add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "
# We still set them here for any DRC checks run in the parent context
# (e.g., report_drc after open_run).
#
# BIVC-1: Bank 14 VCCO=3.3V with LVDS_25 IBUFDS inputs + LVCMOS33 adc_pwdn.
# IBUFDS inputs are VCCO-independent on 7-series (internal diff amplifier).
# The DRC is conservative — aimed at OBUFDS outputs where VCCO affects swing.
# Bank 14 has only LVDS *inputs*, so demoting to warning is safe.
# BIVC-1: Bank 14 VCCO=2.5V (enforced by LVDS_25) with LVCMOS25 adc_pwdn.
# This should no longer fire now that adc_pwdn is LVCMOS25, but we keep
# the waiver as a safety net in case future XDC changes re-introduce the
# conflict.
set_property SEVERITY {Warning} [get_drc_checks BIVC-1]
# NSTD-1 / UCIO-1: 118 unconstrained port bits — FT601 USB 3.0 (chip unwired