fix(pre-bringup): resolve P0 + quick-win P1 findings from 2026-04-19 audit
Addresses findings from docs/DEVELOP_AUDIT_2026-04-19.md: P0 source-level: - F-4.3 ADAR1000_Manager::adarSetTxPhase now writes REG_LOAD_WORKING with LD_WRK_REGS_LDTX_OVERRIDE (0x02) instead of 0x01. Previous value toggled the LDRX latch on a TX-phase write, so host TX phase updates never reached the working registers. - F-6.1 DDC mixer_saturation / filter_overflow / diagnostics were deleted at the receiver boundary. Now plumbed to new outputs on radar_receiver_final (ddc_overflow_any, ddc_saturation_count) and aggregated into gpio_dig5 in radar_system_top. Added mark_debug attributes for ILA visibility. Test/debug inputs tied low explicitly. - F-0.8 adc_clk_mmcm.xdc set_clock_uncertainty: removed invalid -add flag (Vivado silently rejected it, applying zero guardband). Now uses absolute 0.150 ns which covers 53 ps jitter + ~100 ps PVT margin. P1: - F-4.2 adarSetBit / adarResetBit reject broadcast=ON — the RMW sampled a single device but wrote to all four, clobbering the other three's state. - F-4.4 initializeSingleDevice returns false and leaves initialized=false when scratchpad verification fails; previously marked the device initialized anyway so downstream PA enable could drive a dead bus. - F-6.2 FIR I/Q filter_overflow ports, previously unconnected, now OR'd into the module-level filter_overflow output. - F-6.3 mti_canceller exposes 8-bit saturation counter. Saturation was previously invisible and produces spurious Doppler harmonics. Verification: - 27/27 iverilog testbenches pass - 228/228 pytest pass (cross-layer contract + cosim) - MCU unit tests 51/51 + 24/24 pass - Remote Vivado 2025.2 build: bitstream writes; 400 MHz mixer pipeline now shows WNS -0.109 ns which MATCHES the audit's F-0.9 prediction that the design only closed because F-0.8's guardband was silently dropped. ft_clkout F-0.9 remains a show-stopper (requires MRCC pin move), tracked separately. Not addressed in this PR (larger scope, follow-up tickets): F-0.4, F-0.5, F-0.6, F-0.7, F-0.9, F-1.1, F-1.2, F-2.2, F-3.2, F-4.1, F-4.7, F-6.4, F-6.5.
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Jason
@@ -198,6 +198,14 @@ wire [7:0] rx_agc_saturation_count;
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wire [7:0] rx_agc_peak_magnitude;
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wire [3:0] rx_agc_current_gain;
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// DDC overflow diagnostics (audit F-6.1) — plumbed out of receiver so the
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// DDC mixer_saturation / filter_overflow ports are no longer deleted at
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// the boundary. Aggregated into gpio_dig5 alongside AGC saturation.
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wire rx_ddc_overflow_any;
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wire [2:0] rx_ddc_saturation_count;
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// MTI saturation count (audit F-6.3). OR'd into gpio_dig5 for MCU visibility.
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wire [7:0] rx_mti_saturation_count;
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// Data packing for USB
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wire [31:0] usb_range_profile;
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wire usb_range_valid;
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@@ -243,12 +251,12 @@ reg [5:0] host_chirps_per_elev; // Opcode 0x15 (default 32)
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reg host_status_request; // Opcode 0xFF (self-clearing pulse)
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// Fix 4: Doppler/chirps mismatch protection
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// DOPPLER_FRAME_CHIRPS is the fixed chirp count expected by the staggered-PRI
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// Doppler path (16 long + 16 short). If host sets chirps_per_elev to a
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// different value, Doppler accumulation is corrupted. Clamp at command decode
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// and flag the mismatch so the host knows.
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localparam DOPPLER_FRAME_CHIRPS = 32; // Total chirps per Doppler frame
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reg chirps_mismatch_error; // Set if host tried to set chirps != FFT size
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// DOPPLER_FRAME_CHIRPS is the fixed chirp count expected by the staggered-PRI
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// Doppler path (16 long + 16 short). If host sets chirps_per_elev to a
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// different value, Doppler accumulation is corrupted. Clamp at command decode
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// and flag the mismatch so the host knows.
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localparam DOPPLER_FRAME_CHIRPS = 32; // Total chirps per Doppler frame
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reg chirps_mismatch_error; // Set if host tried to set chirps != FFT size
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// Fix 7: Range-mode register (opcode 0x20)
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// Future-proofing for 3km/10km antenna switching.
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@@ -562,7 +570,12 @@ radar_receiver_final rx_inst (
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// AGC status outputs
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.agc_saturation_count(rx_agc_saturation_count),
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.agc_peak_magnitude(rx_agc_peak_magnitude),
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.agc_current_gain(rx_agc_current_gain)
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.agc_current_gain(rx_agc_current_gain),
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// DDC overflow diagnostics (audit F-6.1)
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.ddc_overflow_any(rx_ddc_overflow_any),
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.ddc_saturation_count(rx_ddc_saturation_count),
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// MTI saturation count (audit F-6.3)
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.mti_saturation_count_out(rx_mti_saturation_count)
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);
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// ============================================================================
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@@ -578,21 +591,21 @@ assign rx_doppler_data_valid = rx_doppler_valid;
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// ============================================================================
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// DC NOTCH FILTER (post-Doppler-FFT, pre-CFAR)
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// ============================================================================
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// Zeros out Doppler bins within ±host_dc_notch_width of DC for BOTH
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// sub-frames in the dual 16-pt FFT architecture.
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// doppler_bin[4:0] = {sub_frame, bin[3:0]}:
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// Sub-frame 0: bins 0-15, DC = bin 0, wrap = bin 15
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// Sub-frame 1: bins 16-31, DC = bin 16, wrap = bin 31
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// notch_width=1 → zero bins {0,16}. notch_width=2 → zero bins
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// {0,1,15,16,17,31}. etc.
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// When host_dc_notch_width=0: pass-through (no zeroing).
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wire dc_notch_active;
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wire [4:0] dop_bin_unsigned = rx_doppler_bin;
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wire [3:0] bin_within_sf = dop_bin_unsigned[3:0];
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assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
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(bin_within_sf < {1'b0, host_dc_notch_width} ||
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bin_within_sf > (4'd15 - {1'b0, host_dc_notch_width} + 4'd1));
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// Zeros out Doppler bins within ±host_dc_notch_width of DC for BOTH
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// sub-frames in the dual 16-pt FFT architecture.
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// doppler_bin[4:0] = {sub_frame, bin[3:0]}:
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// Sub-frame 0: bins 0-15, DC = bin 0, wrap = bin 15
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// Sub-frame 1: bins 16-31, DC = bin 16, wrap = bin 31
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// notch_width=1 → zero bins {0,16}. notch_width=2 → zero bins
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// {0,1,15,16,17,31}. etc.
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// When host_dc_notch_width=0: pass-through (no zeroing).
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wire dc_notch_active;
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wire [4:0] dop_bin_unsigned = rx_doppler_bin;
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wire [3:0] bin_within_sf = dop_bin_unsigned[3:0];
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assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
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(bin_within_sf < {1'b0, host_dc_notch_width} ||
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bin_within_sf > (4'd15 - {1'b0, host_dc_notch_width} + 4'd1));
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// Notched Doppler data: zero I/Q when in notch zone, pass through otherwise
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wire [31:0] notched_doppler_data = dc_notch_active ? 32'd0 : rx_doppler_output;
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@@ -959,19 +972,19 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
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8'h13: host_short_chirp_cycles <= usb_cmd_value;
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8'h14: host_short_listen_cycles <= usb_cmd_value;
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8'h15: begin
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// Fix 4: Clamp chirps_per_elev to the fixed Doppler frame size.
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// If host requests a different value, clamp and set error flag.
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if (usb_cmd_value[5:0] > DOPPLER_FRAME_CHIRPS[5:0]) begin
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host_chirps_per_elev <= DOPPLER_FRAME_CHIRPS[5:0];
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chirps_mismatch_error <= 1'b1;
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end else if (usb_cmd_value[5:0] == 6'd0) begin
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host_chirps_per_elev <= DOPPLER_FRAME_CHIRPS[5:0];
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chirps_mismatch_error <= 1'b1;
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end else begin
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host_chirps_per_elev <= usb_cmd_value[5:0];
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// Clear error only if value matches FFT size exactly
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chirps_mismatch_error <= (usb_cmd_value[5:0] != DOPPLER_FRAME_CHIRPS[5:0]);
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end
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// Fix 4: Clamp chirps_per_elev to the fixed Doppler frame size.
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// If host requests a different value, clamp and set error flag.
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if (usb_cmd_value[5:0] > DOPPLER_FRAME_CHIRPS[5:0]) begin
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host_chirps_per_elev <= DOPPLER_FRAME_CHIRPS[5:0];
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chirps_mismatch_error <= 1'b1;
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end else if (usb_cmd_value[5:0] == 6'd0) begin
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host_chirps_per_elev <= DOPPLER_FRAME_CHIRPS[5:0];
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chirps_mismatch_error <= 1'b1;
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end else begin
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host_chirps_per_elev <= usb_cmd_value[5:0];
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// Clear error only if value matches FFT size exactly
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chirps_mismatch_error <= (usb_cmd_value[5:0] != DOPPLER_FRAME_CHIRPS[5:0]);
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end
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end
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8'h16: host_gain_shift <= usb_cmd_value[3:0]; // Fix 3: digital gain
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8'h20: host_range_mode <= usb_cmd_value[1:0]; // Fix 7: range mode
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@@ -1040,7 +1053,13 @@ assign system_status = status_reg;
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// DIG_6: AGC enable flag — mirrors host_agc_enable so STM32 outer-loop AGC
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// tracks the FPGA register as single source of truth.
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// DIG_7: Reserved (tied low for future use).
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assign gpio_dig5 = (rx_agc_saturation_count != 8'd0);
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// gpio_dig5: "signal-chain clipped" — asserts on AGC saturation, DDC mixer/FIR
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// overflow, or MTI 2-pulse saturation. Audit F-6.1/F-6.3: these were all
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// previously invisible to the MCU.
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assign gpio_dig5 = (rx_agc_saturation_count != 8'd0)
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| rx_ddc_overflow_any
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| (rx_ddc_saturation_count != 3'd0)
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| (rx_mti_saturation_count != 8'd0);
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assign gpio_dig6 = host_agc_enable;
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assign gpio_dig7 = 1'b0;
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@@ -1075,4 +1094,4 @@ always @(posedge clk_100m_buf) begin
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end
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`endif
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endmodule
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endmodule
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