fix(pre-bringup): resolve P0 + quick-win P1 findings from 2026-04-19 audit

Addresses findings from docs/DEVELOP_AUDIT_2026-04-19.md:

P0 source-level:
- F-4.3 ADAR1000_Manager::adarSetTxPhase now writes REG_LOAD_WORKING
  with LD_WRK_REGS_LDTX_OVERRIDE (0x02) instead of 0x01. Previous value
  toggled the LDRX latch on a TX-phase write, so host TX phase updates
  never reached the working registers.
- F-6.1 DDC mixer_saturation / filter_overflow / diagnostics were deleted
  at the receiver boundary. Now plumbed to new outputs on
  radar_receiver_final (ddc_overflow_any, ddc_saturation_count) and
  aggregated into gpio_dig5 in radar_system_top. Added mark_debug
  attributes for ILA visibility. Test/debug inputs tied low explicitly.
- F-0.8 adc_clk_mmcm.xdc set_clock_uncertainty: removed invalid -add
  flag (Vivado silently rejected it, applying zero guardband). Now uses
  absolute 0.150 ns which covers 53 ps jitter + ~100 ps PVT margin.

P1:
- F-4.2 adarSetBit / adarResetBit reject broadcast=ON — the RMW sampled
  a single device but wrote to all four, clobbering the other three's
  state.
- F-4.4 initializeSingleDevice returns false and leaves initialized=false
  when scratchpad verification fails; previously marked the device
  initialized anyway so downstream PA enable could drive a dead bus.
- F-6.2 FIR I/Q filter_overflow ports, previously unconnected, now OR'd
  into the module-level filter_overflow output.
- F-6.3 mti_canceller exposes 8-bit saturation counter. Saturation was
  previously invisible and produces spurious Doppler harmonics.

Verification:
- 27/27 iverilog testbenches pass
- 228/228 pytest pass (cross-layer contract + cosim)
- MCU unit tests 51/51 + 24/24 pass
- Remote Vivado 2025.2 build: bitstream writes; 400 MHz mixer pipeline
  now shows WNS -0.109 ns which MATCHES the audit's F-0.9 prediction
  that the design only closed because F-0.8's guardband was silently
  dropped. ft_clkout F-0.9 remains a show-stopper (requires MRCC pin
  move), tracked separately.

Not addressed in this PR (larger scope, follow-up tickets):
F-0.4, F-0.5, F-0.6, F-0.7, F-0.9, F-1.1, F-1.2, F-2.2, F-3.2, F-4.1,
F-4.7, F-6.4, F-6.5.

9_Firmware/9_2_FPGA/ddc_400m.v

@@ -634,6 +634,11 @@ cdc_adc_to_processing #(
 // FIR Filter Instances
 // ============================================================================
 
+// FIR overflow flags (audit F-6.2 — previously dangling, now OR'd into
+// module-level filter_overflow so the receiver can see FIR arithmetic overflow)
+wire fir_i_overflow;
+wire fir_q_overflow;
+
 // FIR I channel
 fir_lowpass_parallel_enhanced fir_i_inst (
     .clk(clk_100m),
@@ -643,10 +648,10 @@ fir_lowpass_parallel_enhanced fir_i_inst (
     .data_out(fir_i_out),
     .data_out_valid(fir_valid_i),
     .fir_ready(fir_i_ready),
-    .filter_overflow()
+    .filter_overflow(fir_i_overflow)
 );
 
-// FIR Q channel  
+// FIR Q channel
 fir_lowpass_parallel_enhanced fir_q_inst (
     .clk(clk_100m),
     .reset_n(reset_n),
@@ -655,10 +660,11 @@ fir_lowpass_parallel_enhanced fir_q_inst (
     .data_out(fir_q_out),
     .data_out_valid(fir_valid_q),
     .fir_ready(fir_q_ready),
-    .filter_overflow()
+    .filter_overflow(fir_q_overflow)
 );
 
 assign fir_valid = fir_valid_i & fir_valid_q;
+assign filter_overflow = fir_i_overflow | fir_q_overflow;
 
 // ============================================================================
 // Enhanced Output Stage