fix(pre-bringup): resolve P0 + quick-win P1 findings from 2026-04-19 audit
Addresses findings from docs/DEVELOP_AUDIT_2026-04-19.md: P0 source-level: - F-4.3 ADAR1000_Manager::adarSetTxPhase now writes REG_LOAD_WORKING with LD_WRK_REGS_LDTX_OVERRIDE (0x02) instead of 0x01. Previous value toggled the LDRX latch on a TX-phase write, so host TX phase updates never reached the working registers. - F-6.1 DDC mixer_saturation / filter_overflow / diagnostics were deleted at the receiver boundary. Now plumbed to new outputs on radar_receiver_final (ddc_overflow_any, ddc_saturation_count) and aggregated into gpio_dig5 in radar_system_top. Added mark_debug attributes for ILA visibility. Test/debug inputs tied low explicitly. - F-0.8 adc_clk_mmcm.xdc set_clock_uncertainty: removed invalid -add flag (Vivado silently rejected it, applying zero guardband). Now uses absolute 0.150 ns which covers 53 ps jitter + ~100 ps PVT margin. P1: - F-4.2 adarSetBit / adarResetBit reject broadcast=ON — the RMW sampled a single device but wrote to all four, clobbering the other three's state. - F-4.4 initializeSingleDevice returns false and leaves initialized=false when scratchpad verification fails; previously marked the device initialized anyway so downstream PA enable could drive a dead bus. - F-6.2 FIR I/Q filter_overflow ports, previously unconnected, now OR'd into the module-level filter_overflow output. - F-6.3 mti_canceller exposes 8-bit saturation counter. Saturation was previously invisible and produces spurious Doppler harmonics. Verification: - 27/27 iverilog testbenches pass - 228/228 pytest pass (cross-layer contract + cosim) - MCU unit tests 51/51 + 24/24 pass - Remote Vivado 2025.2 build: bitstream writes; 400 MHz mixer pipeline now shows WNS -0.109 ns which MATCHES the audit's F-0.9 prediction that the design only closed because F-0.8's guardband was silently dropped. ft_clkout F-0.9 remains a show-stopper (requires MRCC pin move), tracked separately. Not addressed in this PR (larger scope, follow-up tickets): F-0.4, F-0.5, F-0.6, F-0.7, F-0.9, F-1.1, F-1.2, F-2.2, F-3.2, F-4.1, F-4.7, F-6.4, F-6.5.
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Jason
@@ -10,15 +10,15 @@ extern SPI_HandleTypeDef hspi1;
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extern UART_HandleTypeDef huart3;
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// Chip Select GPIO definitions
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static const struct {
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GPIO_TypeDef* port;
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uint16_t pin;
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} CHIP_SELECTS[4] = {
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{ADAR_1_CS_3V3_GPIO_Port, ADAR_1_CS_3V3_Pin}, // ADAR1000 #1
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{ADAR_2_CS_3V3_GPIO_Port, ADAR_2_CS_3V3_Pin}, // ADAR1000 #2
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{ADAR_3_CS_3V3_GPIO_Port, ADAR_3_CS_3V3_Pin}, // ADAR1000 #3
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{ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin} // ADAR1000 #4
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};
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static const struct {
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GPIO_TypeDef* port;
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uint16_t pin;
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} CHIP_SELECTS[4] = {
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{ADAR_1_CS_3V3_GPIO_Port, ADAR_1_CS_3V3_Pin}, // ADAR1000 #1
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{ADAR_2_CS_3V3_GPIO_Port, ADAR_2_CS_3V3_Pin}, // ADAR1000 #2
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{ADAR_3_CS_3V3_GPIO_Port, ADAR_3_CS_3V3_Pin}, // ADAR1000 #3
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{ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin} // ADAR1000 #4
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};
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// ADAR1000 Vector Modulator lookup tables (128-state phase grid, 2.8125 deg step).
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//
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@@ -255,15 +255,15 @@ bool ADAR1000Manager::setBeamAngle(float angle_degrees, BeamDirection direction)
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for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
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for (uint8_t ch = 0; ch < 4; ++ch) {
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if (direction == BeamDirection::TX) {
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adarSetTxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
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adarSetTxVgaGain(dev, ch + 1, kDefaultTxVgaGain, BROADCAST_OFF);
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} else {
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adarSetRxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
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adarSetRxVgaGain(dev, ch + 1, kDefaultRxVgaGain, BROADCAST_OFF);
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}
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}
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}
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if (direction == BeamDirection::TX) {
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adarSetTxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
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adarSetTxVgaGain(dev, ch + 1, kDefaultTxVgaGain, BROADCAST_OFF);
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} else {
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adarSetRxPhase(dev, ch + 1, phase_settings[ch], BROADCAST_OFF);
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adarSetRxVgaGain(dev, ch + 1, kDefaultRxVgaGain, BROADCAST_OFF);
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}
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}
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}
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return true;
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}
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@@ -433,10 +433,15 @@ bool ADAR1000Manager::initializeSingleDevice(uint8_t deviceIndex) {
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adarWrite(deviceIndex, REG_ADC_CONTROL, ADAR1000_ADC_2MHZ_CLK | ADAR1000_ADC_EN, BROADCAST_OFF);
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// Verify communication with scratchpad test
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// Audit F-4.4: on SPI failure, previously marked the device initialized
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// anyway, so downstream (e.g. PA enable) could drive PA gates out-of-spec
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// on a dead bus. Now propagate the failure so initializeAllDevices aborts.
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DIAG("BF", " dev[%u] verifying SPI communication...", deviceIndex);
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bool comms_ok = verifyDeviceCommunication(deviceIndex);
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if (!comms_ok) {
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DIAG_WARN("BF", " dev[%u] scratchpad verify FAILED but marking initialized anyway", deviceIndex);
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DIAG_ERR("BF", " dev[%u] scratchpad verify FAILED -- device NOT marked initialized", deviceIndex);
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devices_[deviceIndex]->initialized = false;
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return false;
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}
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devices_[deviceIndex]->initialized = true;
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@@ -522,7 +527,7 @@ bool ADAR1000Manager::initializeADTR1107Sequence() {
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HAL_UART_Transmit(&huart3, success, sizeof(success) - 1, 1000);
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return true;
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}
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}
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bool ADAR1000Manager::setAllDevicesTXMode() {
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DIAG("BF", "setAllDevicesTXMode(): ADTR1107 -> TX, then configure ADAR1000s");
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@@ -648,7 +653,7 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
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}
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DIAG("BF", " ADTR1107 RX mode complete");
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}
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}
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}
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void ADAR1000Manager::setADTR1107Control(bool tx_mode) {
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DIAG("BF", "setADTR1107Control(%s): setting TR switch on all %u devices, settling %lu us",
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@@ -727,7 +732,7 @@ void ADAR1000Manager::setLNABias(bool enable) {
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for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
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adarWrite(dev, REG_LNA_BIAS_ON, lna_bias, BROADCAST_OFF);
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}
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}
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}
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void ADAR1000Manager::delayUs(uint32_t microseconds) {
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// Simple implementation - for F7 @ 216MHz, each loop ~7 cycles ≈ 0.032us
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@@ -835,12 +840,26 @@ uint8_t ADAR1000Manager::adarRead(uint8_t deviceIndex, uint32_t mem_addr) {
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}
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void ADAR1000Manager::adarSetBit(uint8_t deviceIndex, uint32_t mem_addr, uint8_t bit, uint8_t broadcast) {
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// Audit F-4.2: broadcast-RMW is unsafe. The read samples a single device
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// but the write fans out to all four, overwriting the other three with
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// deviceIndex's state. Reject and surface the mistake.
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if (broadcast == BROADCAST_ON) {
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DIAG_ERR("BF", "adarSetBit: broadcast RMW is unsafe, ignored (dev=%u addr=0x%03lX bit=%u)",
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deviceIndex, (unsigned long)mem_addr, bit);
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return;
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}
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uint8_t temp = adarRead(deviceIndex, mem_addr);
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uint8_t data = temp | (1 << bit);
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adarWrite(deviceIndex, mem_addr, data, broadcast);
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}
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void ADAR1000Manager::adarResetBit(uint8_t deviceIndex, uint32_t mem_addr, uint8_t bit, uint8_t broadcast) {
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// Audit F-4.2: see adarSetBit.
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if (broadcast == BROADCAST_ON) {
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DIAG_ERR("BF", "adarResetBit: broadcast RMW is unsafe, ignored (dev=%u addr=0x%03lX bit=%u)",
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deviceIndex, (unsigned long)mem_addr, bit);
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return;
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}
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uint8_t temp = adarRead(deviceIndex, mem_addr);
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uint8_t data = temp & ~(1 << bit);
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adarWrite(deviceIndex, mem_addr, data, broadcast);
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@@ -904,7 +923,7 @@ void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8
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adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
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adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
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adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
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adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
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}
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void ADAR1000Manager::adarSetRxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
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@@ -929,11 +948,11 @@ void ADAR1000Manager::adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uin
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adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
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}
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void ADAR1000Manager::adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast) {
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adarWrite(deviceIndex, REG_BIAS_CURRENT_TX, kTxBiasCurrent, broadcast);
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adarWrite(deviceIndex, REG_BIAS_CURRENT_TX_DRV, kTxDriverBiasCurrent, broadcast);
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adarWrite(deviceIndex, REG_LOAD_WORKING, 0x2, broadcast);
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}
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void ADAR1000Manager::adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast) {
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adarWrite(deviceIndex, REG_BIAS_CURRENT_TX, kTxBiasCurrent, broadcast);
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adarWrite(deviceIndex, REG_BIAS_CURRENT_TX_DRV, kTxDriverBiasCurrent, broadcast);
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adarWrite(deviceIndex, REG_LOAD_WORKING, 0x2, broadcast);
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}
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uint8_t ADAR1000Manager::adarAdcRead(uint8_t deviceIndex, uint8_t broadcast) {
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adarWrite(deviceIndex, REG_ADC_CONTROL, ADAR1000_ADC_ST_CONV, broadcast);
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