Fix RTL Bug #3: S_IDLE->S_ACCUMULATE now writes first sample immediately

Previously the S_IDLE->S_ACCUMULATE transition consumed one data_valid
cycle without writing to BRAM, losing the first sample. The testbench
worked around this by sending sample[0] twice.

Fix: drive mem_we + data capture in S_IDLE on the transition cycle and
advance write_range_bin to 1. Testbench workaround removed.

Verified: 3/3 Doppler co-sim BIT-PERFECT, integration test 10/10 PASS.

9_Firmware/9_2_FPGA/doppler_processor.v

@@ -206,7 +206,14 @@ always @(posedge clk or negedge reset_n) begin
                 
                 if (data_valid && !frame_buffer_full) begin
                     state <= S_ACCUMULATE;
-                    write_range_bin <= 0;
+                    // Write the first sample immediately (Bug #3 fix:
+                    // previously this transition consumed data_valid
+                    // without writing to BRAM)
+                    mem_we      <= 1;
+                    mem_waddr_r <= mem_write_addr;
+                    mem_wdata_i <= range_data[15:0];
+                    mem_wdata_q <= range_data[31:16];
+                    write_range_bin <= 1;
                 end
             end
             

9_Firmware/9_2_FPGA/tb/tb_doppler_cosim.v

@@ -214,19 +214,10 @@ initial begin
     @(posedge clk);
 
     // ---- Feed input data ----
-    // The RTL FSM consumes one data_valid cycle for the S_IDLE -> S_ACCUMULATE
+    // RTL Bug #3 is now fixed: S_IDLE -> S_ACCUMULATE writes the first
-    // transition without writing data.  We pre-assert data_valid with a dummy
+    // sample immediately, so we simply stream all 2048 samples.
-    // sample to trigger the transition, then stream the 2048 real samples.
     $display("\n--- Feeding %0d input samples ---", TOTAL_INPUTS);
 
-    // Trigger S_IDLE -> S_ACCUMULATE with first real sample
-    // (RTL will see data_valid=1 but NOT write to memory on transition cycle)
-    @(posedge clk);
-    range_data <= input_mem[0];
-    data_valid <= 1;
-
-    // Now stream all 2048 samples — the first one is re-presented since the
-    // transition cycle consumed the first data_valid without writing.
     for (i = 0; i < TOTAL_INPUTS; i = i + 1) begin
         @(posedge clk);
         range_data <= input_mem[i];