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Fix RTL Bug #3: S_IDLE->S_ACCUMULATE now writes first sample immediately

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Previously the S_IDLE->S_ACCUMULATE transition consumed one data_valid
cycle without writing to BRAM, losing the first sample. The testbench
worked around this by sending sample[0] twice.

Fix: drive mem_we + data capture in S_IDLE on the transition cycle and
advance write_range_bin to 1. Testbench workaround removed.

Verified: 3/3 Doppler co-sim BIT-PERFECT, integration test 10/10 PASS.
This commit is contained in:
Jason
2026-03-16 19:08:16 +02:00
parent 2db32af1d0
commit 39f78d4349
2 changed files with 10 additions and 12 deletions
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9_Firmware/9_2_FPGA/doppler_processor.v
+8 -1
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@@ -206,7 +206,14 @@ always @(posedge clk or negedge reset_n) begin
if (data_valid && !frame_buffer_full) begin
state <= S_ACCUMULATE;
write_range_bin <= 0;
// Write the first sample immediately (Bug #3 fix:
// previously this transition consumed data_valid
// without writing to BRAM)
mem_we <= 1;
mem_waddr_r <= mem_write_addr;
mem_wdata_i <= range_data[15:0];
mem_wdata_q <= range_data[31:16];
write_range_bin <= 1;
end
end