fix(fpga): F-0.9 option A — BUFIO+BUFR for 50T ft_clkout (SRCC pin)

C4 is an SRCC pin (IS_CLK_CAPABLE=1, IS_MASTER=0 in the Vivado device model), not an MRCC as earlier comments claimed. SRCC cannot drive BUFG through dedicated routing, so the previous CLOCK_DEDICATED_ROUTE=FALSE override forced fabric routing and burned ~5 ns on the ft_clkout path (WNS -5.362 ns in the d36a4c9 build). Swap to BUFIO + BUFR for USB_MODE=1 (50T/FT2232H): SRCC → BUFIO → BUFR is the standard 7-series path for regional clock distribution. All ft_clkout-domain logic (FT2232H FSM, toggle CDCs, USB FIFO flops) is contained in bank 35 / one clock region, so regional distribution is sufficient. USB_MODE=0 (200T/FT601) keeps the BUFG because D17 is a proper MRCC pin. Removed CLOCK_DEDICATED_ROUTE=FALSE from both the XDC and the build script — no longer needed with dedicated BUFIO/BUFR routing.
2026-04-20 20:53:49 +05:45
parent d36a4c93e2
commit 30279e8c4d
3 changed files with 35 additions and 24 deletions
@@ -111,12 +111,10 @@ set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
 set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
 set_property SEVERITY {Warning} [get_drc_checks PLIO-9]

-# FT2232H CLKOUT on C4 (N-type MRCC) — override dedicated clock route check.
-# The schematic routes the FT2232H 60 MHz clock to the N-pin of a differential
-# MRCC pair. Vivado Place 30-876 requires this property to allow placement.
-# The clock still reaches the clock network via IBUFG — this only suppresses
-# the DRC that demands the P-type pin.
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ft_clkout_IBUF}]
+# FT2232H CLKOUT routing: C4 is SRCC, not MRCC. Earlier builds used
+# CLOCK_DEDICATED_ROUTE=FALSE + implicit BUFG, which forced fabric routing
+# and burned ~5 ns. radar_system_top.v now uses BUFIO+BUFR for USB_MODE=1
+# (regional distribution from SRCC) so the override is no longer required.

 # ---- Run implementation steps ----
 opt_design -directive Explore