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fix(fpga): F-0.9 option A — BUFIO+BUFR for 50T ft_clkout (SRCC pin)

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C4 is an SRCC pin (IS_CLK_CAPABLE=1, IS_MASTER=0 in the Vivado device
model), not an MRCC as earlier comments claimed. SRCC cannot drive BUFG
through dedicated routing, so the previous CLOCK_DEDICATED_ROUTE=FALSE
override forced fabric routing and burned ~5 ns on the ft_clkout path
(WNS -5.362 ns in the d36a4c9 build).

Swap to BUFIO + BUFR for USB_MODE=1 (50T/FT2232H): SRCC → BUFIO → BUFR
is the standard 7-series path for regional clock distribution. All
ft_clkout-domain logic (FT2232H FSM, toggle CDCs, USB FIFO flops) is
contained in bank 35 / one clock region, so regional distribution is
sufficient. USB_MODE=0 (200T/FT601) keeps the BUFG because D17 is a
proper MRCC pin.

Removed CLOCK_DEDICATED_ROUTE=FALSE from both the XDC and the build
script — no longer needed with dedicated BUFIO/BUFR routing.
This commit is contained in:
Jason
2026-04-20 20:53:49 +05:45
parent d36a4c93e2
commit 30279e8c4d
3 changed files with 35 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/radar_system_top.v
+21 -4
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@@ -327,10 +327,27 @@ BUFG bufg_120m (
.O(clk_120m_dac_buf)
);
BUFG bufg_ft601 (
.I(ft601_clk_in),
.O(ft601_clk_buf)
);
// USB clock buffering:
// USB_MODE=0 (200T/FT601): pin is MRCC (D17) → BUFG, global clock network.
// USB_MODE=1 (50T/FT2232H): pin is SRCC (C4, non-MRCC) → BUFIO + BUFR for
// regional dedicated routing. SRCC can drive BUFIO/BUFR but not BUFG
// directly (the "poor placement IO→BUFG" CLOCK_DEDICATED_ROUTE=FALSE
// override was burning ~5 ns in fabric routing on the ft_clkout path).
// All ft_clkout-domain logic (FT2232H FSM, FIFO flops, toggle CDCs) is
// contained in bank 35 / one clock region, so regional distribution
// is sufficient. See UG472 §3 BUFIO/BUFR.
generate if (USB_MODE == 1) begin : gen_ft_bufr
wire ft_clk_bufio;
BUFIO bufio_ft (.I(ft601_clk_in), .O(ft_clk_bufio));
BUFR #(.BUFR_DIVIDE("BYPASS"), .SIM_DEVICE("7SERIES")) bufr_ft (
.I(ft_clk_bufio),
.O(ft601_clk_buf),
.CE(1'b1),
.CLR(1'b0)
);
end else begin : gen_ft_bufg
BUFG bufg_ft601 (.I(ft601_clk_in), .O(ft601_clk_buf));
end endgenerate
`endif
// Reset synchronization (clk_100m domain)