Fix Vivado DRC: consolidate data_pending flags into single always block, fix MMCM LOCKED false_path

usb_data_interface.v: doppler_data_pending and cfar_data_pending were
driven by two always blocks (CDC sync block set them, write FSM cleared
them). Vivado DRC MDRV-1 flagged this as multiple drivers. Moved all
set/clear logic into the write FSM always block using doppler_valid_ft
and cfar_valid_ft edge wires.

adc_clk_mmcm.xdc: changed set_false_path -from to -through for MMCM
LOCKED pin (not a valid timing startpoint). Eliminates CRITICAL WARNING
from Builds 19/20/21.

19/19 FPGA regression pass.

9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc

@@ -56,7 +56,10 @@ set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
 # --------------------------------------------------------------------------
 # MMCM Locked — asynchronous status signal, no timing paths needed
 # --------------------------------------------------------------------------
-set_false_path -from [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
+# LOCKED is not a valid timing startpoint (it's a combinational output of the
+# MMCM primitive). Use -through instead of -from to waive all paths that pass
+# through the LOCKED net. This avoids the CRITICAL WARNING from Build 19/20.
+set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
 
 # --------------------------------------------------------------------------
 # Hold waiver for BUFIO→MMCM domain transfer (if Vivado flags hold violations)