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Fix CFAR blocking assignment (= to <=) in clocked block, add Build 15 analysis report

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CFAR magnitude computation in radar_system_top.v used blocking assignment (=)
inside posedge-clocked always block, creating sim/synth mismatch risk. Changed
to non-blocking (<=). Threshold check now reads previous cycle's magnitude,
which is correct sequential behavior. Regression: 15/15 quick + system TB pass.

Build 15 analysis written to 10_docs/reports/ (not tracked — gitignored).
This commit is contained in:
Jason
2026-03-19 13:22:15 +02:00
parent 3fa26c9e4c
commit 2763b4be91
1 changed files with 2 additions and 2 deletions
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9_Firmware/9_2_FPGA/radar_system_top.v
+2 -2
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@@ -436,8 +436,8 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
// Simple threshold detection on doppler magnitude // Simple threshold detection on doppler magnitude
if (rx_doppler_valid) begin if (rx_doppler_valid) begin
// Calculate approximate magnitude (|I| + |Q|) // Calculate approximate magnitude (|I| + |Q|)
cfar_mag = (rx_doppler_real[15] ? -rx_doppler_real : rx_doppler_real) + cfar_mag <= (rx_doppler_real[15] ? -rx_doppler_real : rx_doppler_real) +
(rx_doppler_imag[15] ? -rx_doppler_imag : rx_doppler_imag); (rx_doppler_imag[15] ? -rx_doppler_imag : rx_doppler_imag);
// Threshold detection // Threshold detection
if (cfar_mag > 17'd10000) begin if (cfar_mag > 17'd10000) begin