refactor(mcu): remove redundant ADAR1000 T/R SPI paths (FPGA-owned)

Per-chirp T/R switching is owned by the FPGA plfm_chirp_controller
driving adar_tr_x pins (TR_SOURCE=1 in REG_SW_CONTROL, already set by
initializeSingleDevice). The MCU's SPI RMW path via fastTXMode/
fastRXMode/pulseTXMode/pulseRXMode/setADTR1107Control was:
  (a) architecturally redundant — raced the FPGA-driven TR line,
  (b) toggled the wrong bit (TR_SOURCE instead of TR_SPI),
  (c) in setFastSwitchMode(true) bundled a datasheet-violating
      PA+LNA-simultaneously-biased side effect.

Removed methods and their backing state (fast_switch_mode_,
switch_settling_time_us_). Call sites in executeChirpSequence /
runRadarPulseSequence updated to rely on the FPGA chirp FSM (GPIOD_8
new_chirp trigger unchanged).

Tests: adds CMSIS-Core DWT/CoreDebug/SystemCoreClock stubs to
stm32_hal_mock so F-4.7's DWT-based delayUs() compiles under the host
mock build. SystemCoreClock=0 makes the busy-wait exit immediately.

9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.c

@@ -406,3 +406,11 @@ static int mock_spi_init_stub(void) { return 0; }
 const struct no_os_spi_platform_ops stm32_spi_ops = {
     .init = mock_spi_init_stub,
 };
+
+/* ========================= CMSIS-Core stub storage ======================= */
+/* See stm32_hal_mock.h for rationale. SystemCoreClock = 0 forces delayUs() to
+ * return immediately under host test builds. DWT->CTRL pre-enabled so the
+ * one-time-init branch is skipped deterministically. */
+struct _DWT_Mock_Type       _dwt_mock       = { .CTRL = DWT_CTRL_CYCCNTENA_Msk, .CYCCNT = 0 };
+struct _CoreDebug_Mock_Type _coredebug_mock = { .DEMCR = 0 };
+uint32_t                    SystemCoreClock = 0U;

9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.h

@@ -242,6 +242,26 @@ uint8_t ADS7830_Measure_SingleEnded(ADC_HandleTypeDef *hadc, uint8_t channel);
  * if desired via a global flag. */
 extern int mock_printf_enabled;
 
+/* ========================= CMSIS-Core stubs ======================= */
+/* Minimum surface to let F-4.7's DWT-based delayUs() in ADAR1000_Manager.cpp
+ * compile under the host mock build. SystemCoreClock is intentionally 0 so
+ * target = microseconds * (SystemCoreClock / 1000000) is also 0, making the
+ * busy-wait loop exit immediately regardless of argument. Pre-setting
+ * DWT->CTRL with CYCCNTENA also skips the one-time init branch.            */
+
+#define DWT_CTRL_CYCCNTENA_Msk     (1UL << 0)
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << 24)
+
+struct _DWT_Mock_Type       { uint32_t CTRL; uint32_t CYCCNT; };
+struct _CoreDebug_Mock_Type { uint32_t DEMCR; };
+
+extern struct _DWT_Mock_Type       _dwt_mock;
+extern struct _CoreDebug_Mock_Type _coredebug_mock;
+extern uint32_t                    SystemCoreClock;
+
+#define DWT       (&_dwt_mock)
+#define CoreDebug (&_coredebug_mock)
+
 #ifdef __cplusplus
 }
 #endif