Improve timing margins with targeted datapath register tuning
Reduce routing pressure on CIC/NCO critical paths and move Doppler BRAM read-address registers to sync-reset datapath logic so Build 13 closes with stronger setup/hold slack while preserving functional behavior.
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@@ -43,7 +43,8 @@ reg [31:0] phase_accum_reg; // Stage 1 output: registered DSP48E1 P[31:0]
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reg [31:0] phase_with_offset; // Stage 2 output: phase_accum_reg + offset
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// Stage 3a pipeline registers: registered LUT address + quadrant
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reg [5:0] lut_index_pipe;
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reg [5:0] lut_index_pipe_sin;
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reg [5:0] lut_index_pipe_cos;
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reg [1:0] quadrant_pipe;
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// Stage 3b pipeline registers: LUT output + quadrant
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@@ -105,8 +106,8 @@ wire [5:0] lut_index = (quadrant_w[0] ^ quadrant_w[1]) ? ~lut_address[5:0] : lut
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// These wires are driven by lut_index_pipe (registered in Stage 3a), so the
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// combinational path is just: lut_index_pipe_reg → LUT6 (distributed RAM read)
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// This eliminates the LUT3→LUT6 two-level critical path from Build 8.
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wire [15:0] sin_abs_w = sin_lut[lut_index_pipe];
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wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe];
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wire [15:0] sin_abs_w = sin_lut[lut_index_pipe_sin];
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wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
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// ============================================================================
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// Stage 1: Phase accumulator (DSP48E1) — accumulates FTW each cycle
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@@ -265,11 +266,13 @@ end
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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lut_index_pipe <= 6'b000000;
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quadrant_pipe <= 2'b00;
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lut_index_pipe_sin <= 6'b000000;
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lut_index_pipe_cos <= 6'b000000;
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quadrant_pipe <= 2'b00;
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end else if (valid_pipe[1]) begin
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lut_index_pipe <= lut_index;
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quadrant_pipe <= quadrant_w;
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lut_index_pipe_sin <= lut_index;
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lut_index_pipe_cos <= lut_index;
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quadrant_pipe <= quadrant_w;
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end
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end
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