fix: close all FPGA timing — CFAR pipeline + CIC reset path (Build 19)

CFAR pipeline fix (clk_100m WNS: -0.331ns → +0.156ns):
- Pre-register col_buf reads during ST_CFAR_THR pipeline stage
- 8 pipeline registers (4 values + 4 valids) break 15-level mux tree
- Delta wires use registered values, eliminating combinatorial depth

CIC reset path fix (clk_mmcm_out0 WNS: -0.074ns → +0.068ns):
- Add reset_h input port to cic_decimator_4x_enhanced.v
- Remove internal wire reset_h = ~reset_n (LUT1 inverter was root cause)
- Wire pre-registered reset_400m from ddc_400m.v into both CIC instances
- 3 sync reset blocks changed from if(!reset_n) to if(reset_h)

Build 19 results (xc7a50tftg256-2, Vivado 2025.2):
- All 5 clock domains timing met, 0 failing endpoints
- WNS: +0.068ns (400MHz), +0.156ns (100MHz), +0.627ns (120MHz)
- Utilization: 66.67% LUT, 22.36% FF, 74% BRAM, 93.33% DSP
- Bitstream: 2,140 KB

9_Firmware/9_2_FPGA/ddc_400m.v

@@ -565,7 +565,8 @@ wire cic_valid_i, cic_valid_q;
 
 cic_decimator_4x_enhanced cic_i_inst (
     .clk(clk_400m),
-    .reset_n(reset_n_400m),
+    .reset_n(reset_n_400m),
+    .reset_h(reset_400m),
     .data_in(mixed_i[33:16]),
     .data_valid(mixed_valid),
     .data_out(cic_i_out),
@@ -574,7 +575,8 @@ cic_decimator_4x_enhanced cic_i_inst (
 
 cic_decimator_4x_enhanced cic_q_inst (
     .clk(clk_400m),
-    .reset_n(reset_n_400m),
+    .reset_n(reset_n_400m),
+    .reset_h(reset_400m),
     .data_in(mixed_q[33:16]),
     .data_valid(mixed_valid),
     .data_out(cic_q_out),