fix(scripts): switch 50T build to non-project-mode impl + remove unconstrained ports
The 50T FTG256 has only 69 usable IO pins but the RTL declares 182 port bits. launch_runs spawns a child process that cannot remove ports. Switch to direct opt_design/place_design/route_design flow so we can remove 118 unconstrained ports (FT601 USB, dac_clk, status/debug) from the netlist before placement, avoiding [Place 30-58] IO overflow.
This commit is contained in:
Jason
@@ -48,11 +48,10 @@ add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "
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# ============================================================================
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# DRC SEVERITY WAIVERS — 50T Hardware-Specific
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# ============================================================================
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# NOTE: set_property SEVERITY in the parent process does NOT propagate to
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# child processes spawned by launch_runs. The actual waivers are applied via
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# a TCL.PRE hook (STEPS.OPT_DESIGN.TCL.PRE) written dynamically below.
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# We still set them here for any DRC checks run in the parent context
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# (e.g., report_drc after open_run).
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# NOTE: DRC severity waivers are set both before synthesis and after open_run
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# synth_1. Implementation uses direct commands (opt_design, place_design, etc.)
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# rather than launch_runs/wait_on_run, so all commands share the same Vivado
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# context. This also allows removing unconstrained ports before placement.
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#
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# BIVC-1: Bank 14 VCCO=2.5V (enforced by LVDS_25) with LVCMOS25 adc_pwdn.
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# This should no longer fire now that adc_pwdn is LVCMOS25, but we keep
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@@ -84,63 +83,68 @@ if {![string match "*Complete*" $synth_status]} {
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open_run synth_1
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report_timing_summary -file "${report_dir}/01_timing_post_synth.rpt"
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report_utilization -file "${report_dir}/01_utilization_post_synth.rpt"
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close_design
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# ===== IMPLEMENTATION =====
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# ===== IMPLEMENTATION (non-project-mode style) =====
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# We run implementation steps directly in the parent process instead of
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# using launch_runs/wait_on_run. This ensures DRC waivers and port removal
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# commands execute in the same Vivado context as place_design.
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set impl_start [clock seconds]
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# Write DRC waiver hook — this runs inside the impl_1 child process
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# right before opt_design, ensuring BIVC-1/NSTD-1/UCIO-1 are demoted
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# to warnings for the DRC checks that gate place_design.
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set hook_file [file join $project_dir "drc_waivers_50t.tcl"]
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set fh [open $hook_file w]
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puts $fh "# Auto-generated DRC waiver hook for 50T impl_1"
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puts $fh "set_property SEVERITY {Warning} \[get_drc_checks BIVC-1\]"
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puts $fh "set_property SEVERITY {Warning} \[get_drc_checks NSTD-1\]"
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puts $fh "set_property SEVERITY {Warning} \[get_drc_checks UCIO-1\]"
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puts $fh "puts \" DRC waivers applied (BIVC-1, NSTD-1, UCIO-1 -> Warning)\""
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close $fh
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# Re-apply DRC waivers in this context (parent process)
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set_property SEVERITY {Warning} [get_drc_checks BIVC-1]
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set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
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set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
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set_property STEPS.OPT_DESIGN.TCL.PRE $hook_file [get_runs impl_1]
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set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
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set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
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set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
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set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
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set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE Explore [get_runs impl_1]
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set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
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set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.DIRECTIVE AggressiveExplore [get_runs impl_1]
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launch_runs impl_1 -jobs 8
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wait_on_run impl_1
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set impl_elapsed [expr {[clock seconds] - $impl_start}]
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set impl_status [get_property STATUS [get_runs impl_1]]
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puts " Implementation status: $impl_status"
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puts " Implementation time: ${impl_elapsed}s"
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if {![string match "*Complete*" $impl_status] && ![string match "*write_bitstream*" $impl_status]} {
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puts "CRITICAL: IMPLEMENTATION FAILED: $impl_status"
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close_project
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exit 1
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# ---- Remove unconstrained ports from netlist ----
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# The 50T board (FTG256, 69 usable IOs) cannot accommodate all 182 port bits.
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# These ports have no physical connections on the 50T PCB: FT601 USB 3.0
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# (chip unwired), dac_clk (driven by AD9523, not FPGA), and all
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# status/debug outputs. Removing them from the netlist avoids [Place 30-58].
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set unconstrained_ports {
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ft601_clk_in ft601_data ft601_be ft601_txe_n ft601_rxf_n
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ft601_txe ft601_rxf ft601_wr_n ft601_rd_n ft601_oe_n
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ft601_siwu_n ft601_srb ft601_swb ft601_clk_out
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dac_clk
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current_elevation current_azimuth current_chirp new_chirp_frame
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dbg_doppler_data dbg_doppler_valid dbg_doppler_bin dbg_range_bin
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system_status
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}
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set removed_count 0
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foreach p $unconstrained_ports {
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# Match scalar port or bus port bits (e.g., "ft601_data" matches ft601_data[*])
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set port_objs [get_ports -quiet "${p}\[*\]"]
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if {[llength $port_objs] == 0} {
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set port_objs [get_ports -quiet $p]
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}
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foreach port_obj $port_objs {
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if {[catch {remove_port $port_obj} err]} {
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puts " WARN: Could not remove port $port_obj: $err"
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} else {
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incr removed_count
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}
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}
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}
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puts " Removed $removed_count unconstrained port(s) from netlist"
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# ---- Run implementation steps ----
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opt_design -directive Explore
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place_design -directive Explore
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phys_opt_design -directive AggressiveExplore
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route_design -directive Explore
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phys_opt_design -directive AggressiveExplore
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set impl_elapsed [expr {[clock seconds] - $impl_start}]
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puts " Implementation time: ${impl_elapsed}s"
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# ===== BITSTREAM =====
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set bit_start [clock seconds]
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if {[catch {launch_runs impl_1 -to_step write_bitstream -jobs 8} launch_err]} {
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puts " Note: write_bitstream may already be in progress: $launch_err"
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}
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wait_on_run impl_1
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set bit_elapsed [expr {[clock seconds] - $bit_start}]
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open_run impl_1
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# Copy bitstream
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set src_bit [file join $project_dir "${project_name}.runs" "impl_1" "radar_system_top.bit"]
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set dst_bit [file join $bit_dir "radar_system_top_50t.bit"]
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if {[file exists $src_bit]} {
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file copy -force $src_bit $dst_bit
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puts " Bitstream: $dst_bit"
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write_bitstream -force $dst_bit
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set bit_elapsed [expr {[clock seconds] - $bit_start}]
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if {[file exists $dst_bit]} {
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puts " Bitstream: $dst_bit ([expr {[file size $dst_bit] / 1024}] KB)"
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} else {
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puts " WARNING: Bitstream not found at $src_bit"
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puts " WARNING: Bitstream not generated!"
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}
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# ===== REPORTS =====
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