fix: enforce strict ruff lint (17 rule sets) across entire repo

- Expand ruff config from E/F to 17 rule sets (B, RUF, SIM, PIE, T20,
  ARG, ERA, A, BLE, RET, ISC, TCH, UP, C4, PERF)
- Fix 907 lint errors across all Python files (GUI, FPGA cosim,
  schematics scripts, simulations, utilities, tools)
- Replace all blind except-Exception with specific exception types
- Remove commented-out dead code (ERA001) from cosim/simulation files
- Modernize typing: deprecated typing.List/Dict/Tuple to builtins
- Fix unused args/loop vars, ambiguous unicode, perf anti-patterns
- Delete legacy GUI files V1-V4
- Add V7 test suite, requirements files
- All CI jobs pass: ruff (0 errors), py_compile, pytest (92/92),
  MCU tests (20/20), FPGA regression (25/25)

This commit is contained in:

Jason

2026-04-12 14:18:34 +05:45

parent b6e8eda130

commit 2106e24952

54 changed files with 4619 additions and 9063 deletions

									
										5_Simulations/Fencing/Via_fencing.py
									
		+1
		-2
	
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				@@ -1,7 +1,6 @@

				import matplotlib.pyplot as plt

				# Dimensions (all in mm)

				line_width = 0.204

				line_width = 0.204

				substrate_height = 0.102

				via_drill = 0.20

				via_pad_A = 0.20  # minimal pad case