fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

- Remove xfft_32.v, tb_xfft_32.v, and fft_twiddle_32.mem (dead code
  since PR #33 moved Doppler to dual 16-pt FFT architecture)
- Update run_regression.sh: xfft_16 in PROD_RTL, remove xfft_32 from
  EXTRA_RTL and all compile commands
- Update tb_fft_engine.v to test with N=16 / fft_twiddle_16.mem
- Update validate_mem_files.py: validate fft_twiddle_16.mem instead of 32
- Update testbenches and golden data from main_cleanup branch to match
  dual-16 architecture (tb_doppler_cosim, tb_doppler_realdata,
  tb_fullchain_realdata, tb_fullchain_mti_cfar_realdata, tb_system_e2e,
  radar_receiver_final, golden_doppler.mem)
- Update CONTRIBUTING.md with full regression test instructions covering
  FPGA, MCU, GUI, co-simulation, and formal verification

Regression: 23/23 FPGA, 20/20 MCU, 57/58 GUI, 56/56 mem validation,
all co-sim scenarios PASS.

9_Firmware/9_2_FPGA/xfft_16.v

@@ -5,7 +5,7 @@
 // Wraps the synthesizable fft_engine (radix-2 DIT) with the AXI-Stream port
 // interface expected by the doppler_processor dual-FFT architecture.
 //
-// Identical interface to xfft_32.v but with N=16.
+// Used by the doppler_processor dual-FFT architecture (2 x 16-pt sub-frames).
 //
 // Data format: {Q[15:0], I[15:0]} packed 32-bit.
 // Config tdata[0]: 1 = forward FFT, 0 = inverse FFT.