fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

- Remove xfft_32.v, tb_xfft_32.v, and fft_twiddle_32.mem (dead code
  since PR #33 moved Doppler to dual 16-pt FFT architecture)
- Update run_regression.sh: xfft_16 in PROD_RTL, remove xfft_32 from
  EXTRA_RTL and all compile commands
- Update tb_fft_engine.v to test with N=16 / fft_twiddle_16.mem
- Update validate_mem_files.py: validate fft_twiddle_16.mem instead of 32
- Update testbenches and golden data from main_cleanup branch to match
  dual-16 architecture (tb_doppler_cosim, tb_doppler_realdata,
  tb_fullchain_realdata, tb_fullchain_mti_cfar_realdata, tb_system_e2e,
  radar_receiver_final, golden_doppler.mem)
- Update CONTRIBUTING.md with full regression test instructions covering
  FPGA, MCU, GUI, co-simulation, and formal verification

Regression: 23/23 FPGA, 20/20 MCU, 57/58 GUI, 56/56 mem validation,
all co-sim scenarios PASS.
This commit is contained in:
Jason
2026-04-07 02:51:48 +03:00
parent 04982a3176
commit 1e284767cd
15 changed files with 2265 additions and 2806 deletions
+7 -11
View File
@@ -67,7 +67,7 @@ PROD_RTL=(
matched_filter_processing_chain.v
range_bin_decimator.v
doppler_processor.v
xfft_32.v
xfft_16.v
fft_engine.v
usb_data_interface.v
edge_detector.v
@@ -369,7 +369,7 @@ run_test "Chirp Contract" \
run_test "Doppler Processor (DSP48)" \
tb/tb_doppler_reg.vvp \
tb/tb_doppler_cosim.v doppler_processor.v xfft_32.v fft_engine.v
tb/tb_doppler_cosim.v doppler_processor.v xfft_16.v fft_engine.v
run_test "Threshold Detector (detection bugs)" \
tb/tb_threshold_detector.vvp \
@@ -414,7 +414,7 @@ if [[ "$QUICK" -eq 0 ]]; then
cdc_modules.v fir_lowpass.v ddc_input_interface.v \
chirp_memory_loader_param.v latency_buffer.v \
matched_filter_multi_segment.v matched_filter_processing_chain.v \
range_bin_decimator.v doppler_processor.v xfft_32.v fft_engine.v \
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
rx_gain_control.v mti_canceller.v
# Golden compare
@@ -426,7 +426,7 @@ if [[ "$QUICK" -eq 0 ]]; then
cdc_modules.v fir_lowpass.v ddc_input_interface.v \
chirp_memory_loader_param.v latency_buffer.v \
matched_filter_multi_segment.v matched_filter_processing_chain.v \
range_bin_decimator.v doppler_processor.v xfft_32.v fft_engine.v \
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
rx_gain_control.v mti_canceller.v
# Full system top (monitoring-only, legacy)
@@ -439,7 +439,7 @@ if [[ "$QUICK" -eq 0 ]]; then
cdc_modules.v fir_lowpass.v ddc_input_interface.v \
chirp_memory_loader_param.v latency_buffer.v \
matched_filter_multi_segment.v matched_filter_processing_chain.v \
range_bin_decimator.v doppler_processor.v xfft_32.v fft_engine.v \
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
usb_data_interface.v edge_detector.v radar_mode_controller.v \
rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
@@ -453,7 +453,7 @@ if [[ "$QUICK" -eq 0 ]]; then
cdc_modules.v fir_lowpass.v ddc_input_interface.v \
chirp_memory_loader_param.v latency_buffer.v \
matched_filter_multi_segment.v matched_filter_processing_chain.v \
range_bin_decimator.v doppler_processor.v xfft_32.v fft_engine.v \
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
usb_data_interface.v edge_detector.v radar_mode_controller.v \
rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
else
@@ -472,10 +472,6 @@ run_test "FFT Engine" \
tb/tb_fft_reg.vvp \
tb/tb_fft_engine.v fft_engine.v
run_test "XFFT-32 Wrapper" \
tb/tb_xfft_reg.vvp \
tb/tb_xfft_32.v xfft_32.v fft_engine.v
run_test "NCO 400MHz" \
tb/tb_nco_reg.vvp \
tb/tb_nco_400m.v nco_400m_enhanced.v
@@ -487,7 +483,7 @@ run_test "FIR Lowpass" \
run_test "Matched Filter Chain" \
tb/tb_mf_reg.vvp \
tb/tb_matched_filter_processing_chain.v matched_filter_processing_chain.v \
xfft_32.v fft_engine.v chirp_memory_loader_param.v
fft_engine.v chirp_memory_loader_param.v
echo ""