Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

Production FPGA: Artix-7 XC7A200T-2FBG484I (33,650 slices, 740 DSP48E1,
365 BRAM, -2 speed grade). Pin-mapped across 6 banks with proper VCCO
assignment (3.3V/2.5V/1.8V).

RTL timing primitives added for clean timing closure:
- ad9484_interface_400m.v: BUFIO for IDDR capture at 400MHz DDR,
  BUFG for fabric logic, reset synchronizer (P1-7)
- dac_interface_single.v: ODDR for dac_clk forwarding + dac_data[7:0]
  output registration, eliminates clock-forwarding insertion delay
- usb_data_interface.v: ODDR for ft601_clk_out forwarding, FSM runs
  on ft601_clk_in domain with CDC synchronizers

Constraints:
- New production XDC (xc7a200t_fbg484.xdc): 182 pins, generated clocks
  for ODDR outputs, BUFIO/DDR input delays, fixed false_path strategy
  (from reset source, not to CLR pins), IOB packing on cells not ports
- Preserved upstream XDC as xc7a50t_ftg256.xdc for reference
- Updated cntrt.xdc with DRC fixes (I/O standards, missing constraints)

9_Firmware/9_2_FPGA/dac_interface_single.v

@@ -3,24 +3,79 @@ module dac_interface_enhanced (
     input wire reset_n,
     input wire [7:0] chirp_data,
     input wire chirp_valid,
-    output reg [7:0] dac_data,
+    output wire [7:0] dac_data,
     output wire dac_clk,
-	output wire dac_sleep
+    output wire dac_sleep
 );
 
-// Register DAC data to meet timing
+// ============================================================================
+// DAC data register (fabric FF — feeds ODDR D1/D2 inputs)
+// ============================================================================
+reg [7:0] dac_data_reg;
+
 always @(posedge clk_120m or negedge reset_n) begin
     if (!reset_n) begin
-        dac_data <= 8'd128;  // Center value
+        dac_data_reg <= 8'd128;  // Center value
     end else if (chirp_valid) begin
-        dac_data <= chirp_data;
+        dac_data_reg <= chirp_data;
     end else begin
-        dac_data <= 8'd128;  // Default to center when no chirp
+        dac_data_reg <= 8'd128;  // Default to center when no chirp
     end
 end
 
-// DAC clock is same as input clock (120MHz)
+`ifndef SIMULATION
+// ============================================================================
+// ODDR for dac_clk forwarding (Xilinx 7-series)
+// D1=1, D2=0 produces a clock replica aligned to clk_120m rising edge.
+// The ODDR is placed in the IOB, giving near-zero skew between the
+// forwarded clock and ODDR data outputs in the same bank.
+// ============================================================================
+ODDR #(
+    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
+    .INIT(1'b0),
+    .SRTYPE("SYNC")
+) oddr_dac_clk (
+    .Q(dac_clk),
+    .C(clk_120m),
+    .CE(1'b1),
+    .D1(1'b1),
+    .D2(1'b0),
+    .R(1'b0),
+    .S(1'b0)
+);
+
+// ============================================================================
+// ODDR for dac_data[7:0] — packs output FFs into IOBs
+// D1=D2=same value → SDR behavior through ODDR, but placed in IOB.
+// This eliminates fabric routing delay to the output pad.
+// ============================================================================
+genvar i;
+generate
+    for (i = 0; i < 8; i = i + 1) begin : oddr_dac_data_gen
+        ODDR #(
+            .DDR_CLK_EDGE("OPPOSITE_EDGE"),
+            .INIT(1'b0),
+            .SRTYPE("SYNC")
+        ) oddr_dac_data (
+            .Q(dac_data[i]),
+            .C(clk_120m),
+            .CE(1'b1),
+            .D1(dac_data_reg[i]),
+            .D2(dac_data_reg[i]),
+            .R(1'b0),
+            .S(1'b0)
+        );
+    end
+endgenerate
+
+`else
+// ============================================================================
+// Simulation behavioral equivalent
+// ============================================================================
 assign dac_clk = clk_120m;
+assign dac_data = dac_data_reg;
+`endif
+
 assign dac_sleep = 1'b0;
 
 endmodule