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Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21

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Build 21 Vivado results extracted and documented:
- WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns (all timing met)
- 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%)
- Total power: 0.732 W
- Barrel-shift twiddle freed 1 DSP (140 -> 139) as expected
- TCL script fix: wrap check_timing in catch (Vivado 2025.2 bug)
- Updated release-notes.html, implementation-log.html, reports.html
This commit is contained in:
Jason
2026-03-20 02:21:33 +02:00
parent 2efab23cd9
commit 19284ac277
4 changed files with 28 additions and 13 deletions
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docs/reports.html
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<section class="card" style="margin-top:0.8rem;">
<h2>Current FPGA implementation status</h2>
<ul>
<li><strong>Build 20 (v0.1.3-build20)</strong> is the current production baseline for the XC7A200T target. All timing constraints met: WNS +0.426 ns, WHS +0.058 ns, WPWS +0.361 ns.</li>
<li>Utilization: 6,092 LUTs (4.5%), 9,024 FFs (3.4%), 16 BRAM (4.4%), 140 DSP48E1 (18.9%), 0.730 W total power.</li>
<li>Key improvements over Build 18: 400 MHz MMCM jitter cleaner, CIC comb DSP48E1 CREG pipeline, XDC clock-name fix. Setup slack improved 7x.</li>
<li>Build 20 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build20/</code>.</li>
<li><strong>Build 21 (v0.1.4-build21)</strong> is the current production baseline for the XC7A200T target. All timing constraints met: WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns.</li>
<li>Utilization: 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%), 0.732 W total power.</li>
<li>Key improvements over Build 20: FFT 4-cycle butterfly (20% throughput gain), barrel-shift twiddle index (-1 DSP48), Gap 2 GUI Settings (runtime chirp timing, stream control, status readback), E2E RTL fixes, Vivado DRC multiple-driver fix, MMCM LOCKED XDC false_path correction.</li>
<li>Build 21 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build21/</code>.</li>
</ul>
</section>
@@ -92,9 +92,9 @@
<section class="card" style="margin-top:0.8rem;">
<h2>FPGA implementation analysis</h2>
<p><span class="chip">Status: Current engineering baseline &mdash; Build 20 (v0.1.3-build20)</span></p>
<p class="muted">Build 20 is the current production baseline. Full timing, utilization, power, DRC, methodology, CDC, and route reports are available on the remote Vivado host. Setup slack improved 7x from Build 18 (+0.062 ns to +0.426 ns) via MMCM jitter cleaner, CIC CREG pipeline, and XDC clock-name fix.</p>
<p class="muted">Build 18 (v0.1.2-build18) retained as prior reference. Build 19 failed timing (WNS -0.011 ns) due to conflicting XDC generated clock, root-caused and fixed in Build 20.</p>
<p><span class="chip">Status: Current engineering baseline &mdash; Build 21 (v0.1.4-build21)</span></p>
<p class="muted">Build 21 is the current production baseline. Full timing, utilization, power, DRC, methodology, CDC, and route reports are available on the remote Vivado host. Setup slack is +0.156 ns (tighter than Build 20's +0.426 ns due to Gap 2 register map additions, but comfortable and better than the intermediate Gap 2 build at +0.078 ns). Hold slack improved to +0.064 ns. DSP count dropped from 140 to 139 via barrel-shift twiddle optimization.</p>
<p class="muted">Build 20 (v0.1.3-build20) retained as prior reference. Build 19 failed timing (WNS -0.011 ns) due to conflicting XDC generated clock, root-caused and fixed in Build 20.</p>
</section>
<section class="card" style="margin-top:0.8rem;">
@@ -111,11 +111,11 @@
<section class="card" style="margin-top:0.8rem;">
<h2>Report Currency Notice</h2>
<ul>
<li>The current routed production-target baseline is <strong>Build 20 (v0.1.3-build20)</strong> with all timing constraints met and 7x setup slack improvement over Build 18.</li>
<li>The current routed production-target baseline is <strong>Build 21 (v0.1.4-build21)</strong> with all timing constraints met. WNS +0.156 ns, WHS +0.064 ns, 139 DSP48E1, 0.732 W.</li>
<li>Architectural gaps 2 (GUI Settings), 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR) and 6 (CDC-15) remain for post-bring-up.</li>
<li>FPGA regression: 19/19 pass (includes new E2E integration test). MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).</li>
<li>FFT engine optimized: 4-cycle butterfly (20% throughput gain) + barrel-shift twiddle index (frees 1 DSP48). Pending Vivado build verification.</li>
<li>Detailed Build 20 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build20/</code>.</li>
<li>FFT engine optimized and Vivado-verified in Build 21: 4-cycle butterfly (20% throughput gain) + barrel-shift twiddle index (freed 1 DSP48, 140 &rarr; 139).</li>
<li>Detailed Build 21 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build21/</code>.</li>
<li>The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.</li>
</ul>
</section>