Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21
Build 21 Vivado results extracted and documented: - WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns (all timing met) - 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%) - Total power: 0.732 W - Barrel-shift twiddle freed 1 DSP (140 -> 139) as expected - TCL script fix: wrap check_timing in catch (Vivado 2025.2 bug) - Updated release-notes.html, implementation-log.html, reports.html
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Jason
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<section class="card" style="margin-top:0.8rem;">
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<h2>Recent milestone timeline</h2>
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<div class="timeline">
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<article>
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<h3>Build 21 tagged v0.1.4-build21 — new production baseline (2efab23)</h3>
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<p class="muted">WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns. 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%), 0.732 W. Includes FFT 4-cycle butterfly (20% throughput), barrel-shift twiddle (-1 DSP), Gap 2 GUI Settings, E2E RTL fixes (mixer sequencing, USB data-pending, receiver toggle wiring), Vivado DRC multiple-driver fix for data_pending flags, and MMCM LOCKED XDC false_path correction (-from → -through). Build script crash at report_exceptions/check_timing (Vivado 2025.2 bug) fixed by wrapping in catch blocks; all 12 critical reports and bitstream generated successfully.</p>
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</article>
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<article>
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<h3>E2E integration test + RTL fixes: mixer sequencing, USB data-pending, receiver wiring (0773001)</h3>
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<p class="muted">New end-to-end testbench (tb_system_e2e.v) with 46 checks across 12 groups covering reset, TX, safety, RX, USB R/W, CDC, beam scanning, reset recovery, stream control, latency budgets, and watchdog. RTL fixes discovered via E2E: chirp controller TX/RX mixer enables now mutually exclusive by FSM state; USB write FSM gains doppler/cfar data_pending sticky flags with stream-control reset default changed to range-only (3'b001); receiver gets STM32 toggle signal inputs and dynamic frame detection. USB unit tests 21/22/56 updated for data_pending architecture. Regression script PASS/FAIL parsing hardened. 19/19 FPGA, 20/20 MCU.</p>
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<article class="card">
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<h2>Build history and timing improvements</h2>
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<ul>
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<li><strong>Build 20 (v0.1.3-build20)</strong>: Current production baseline. WNS +0.426 ns, WHS +0.058 ns. 400 MHz MMCM + CIC CREG pipeline. 0.730 W.</li>
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<li><strong>Build 21 (v0.1.4-build21)</strong>: Current production baseline. WNS +0.156 ns, WHS +0.064 ns. FFT 4-cycle butterfly + barrel-shift twiddle. 139 DSP48E1 (-1). 0.732 W.</li>
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<li><strong>Build 20 (v0.1.3-build20)</strong>: Prior production baseline. WNS +0.426 ns, WHS +0.058 ns. 400 MHz MMCM + CIC CREG pipeline. 0.730 W.</li>
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<li><strong>Build 19</strong>: Failed (WNS -0.011 ns). Root cause: conflicting XDC generated clock prevented false-path application.</li>
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<li><strong>Build 18 (v0.1.2-build18)</strong>: Prior baseline. WNS +0.062 ns, WHS +0.059 ns. 0.631 W.</li>
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<li><strong>Build 17 (v0.1.1-build17)</strong>: FIR DSP48 pipelining + matched filter BRAM migration.</li>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td><code>2efab23</code> <strong>v0.1.4-build21</strong></td>
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<td>Build 21: FFT opts + E2E RTL fixes + Vivado DRC fix + MMCM LOCKED false_path fix</td>
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<td>New production baseline. WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns. 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%), 0.732 W. Includes 4-cycle FFT butterfly (20% throughput), barrel-shift twiddle (-1 DSP), Vivado DRC multiple-driver fix for data_pending flags, MMCM LOCKED XDC false_path fix (-from → -through). 19/19 FPGA, 20/20 MCU.</td>
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</tr>
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<tr>
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<td><code>0773001</code></td>
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<td>E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring</td>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Tagged releases</h2>
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<ul>
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<li><strong>v0.1.3-build20</strong> (c6103b3) — Current production baseline. WNS +0.426 ns, all timing met. Includes Gaps 3, 5, 7.</li>
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<li><strong>v0.1.4-build21</strong> (2efab23) — Current production baseline. WNS +0.156 ns, WHS +0.064 ns. Includes FFT opts, E2E RTL fixes, Vivado DRC fix, MMCM LOCKED XDC fix. 139 DSP48E1 (-1 vs Build 20).</li>
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<li><strong>v0.1.3-build20</strong> (c6103b3) — Prior production baseline. WNS +0.426 ns, all timing met. Includes Gaps 3, 5, 7.</li>
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<li><strong>v0.1.2-build18</strong> (3b7afba) — Prior production baseline. WNS +0.062 ns.</li>
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<li><strong>v0.1.1-build17</strong> (ed6f79c) — FIR DSP48 + BRAM migration build.</li>
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<li><strong>v0.1.0-bringup</strong> — Initial bring-up tag.</li>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Open in GitHub</h2>
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<ul>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/2efab23" target="_blank" rel="noopener">2efab23</a> Build 21: FFT opts + DRC fix + XDC fix (v0.1.4-build21)</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/0773001" target="_blank" rel="noopener">0773001</a> E2E test + RTL fixes</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/a3e1996" target="_blank" rel="noopener">a3e1996</a> FFT engine optimizations</li>
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<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/7cdfa48" target="_blank" rel="noopener">7cdfa48</a> Gap 2 GUI Settings</li>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Current FPGA implementation status</h2>
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<ul>
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<li><strong>Build 20 (v0.1.3-build20)</strong> is the current production baseline for the XC7A200T target. All timing constraints met: WNS +0.426 ns, WHS +0.058 ns, WPWS +0.361 ns.</li>
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<li>Utilization: 6,092 LUTs (4.5%), 9,024 FFs (3.4%), 16 BRAM (4.4%), 140 DSP48E1 (18.9%), 0.730 W total power.</li>
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<li>Key improvements over Build 18: 400 MHz MMCM jitter cleaner, CIC comb DSP48E1 CREG pipeline, XDC clock-name fix. Setup slack improved 7x.</li>
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<li>Build 20 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build20/</code>.</li>
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<li><strong>Build 21 (v0.1.4-build21)</strong> is the current production baseline for the XC7A200T target. All timing constraints met: WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns.</li>
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<li>Utilization: 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%), 0.732 W total power.</li>
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<li>Key improvements over Build 20: FFT 4-cycle butterfly (20% throughput gain), barrel-shift twiddle index (-1 DSP48), Gap 2 GUI Settings (runtime chirp timing, stream control, status readback), E2E RTL fixes, Vivado DRC multiple-driver fix, MMCM LOCKED XDC false_path correction.</li>
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<li>Build 21 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build21/</code>.</li>
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</ul>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>FPGA implementation analysis</h2>
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<p><span class="chip">Status: Current engineering baseline — Build 20 (v0.1.3-build20)</span></p>
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<p class="muted">Build 20 is the current production baseline. Full timing, utilization, power, DRC, methodology, CDC, and route reports are available on the remote Vivado host. Setup slack improved 7x from Build 18 (+0.062 ns to +0.426 ns) via MMCM jitter cleaner, CIC CREG pipeline, and XDC clock-name fix.</p>
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<p class="muted">Build 18 (v0.1.2-build18) retained as prior reference. Build 19 failed timing (WNS -0.011 ns) due to conflicting XDC generated clock, root-caused and fixed in Build 20.</p>
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<p><span class="chip">Status: Current engineering baseline — Build 21 (v0.1.4-build21)</span></p>
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<p class="muted">Build 21 is the current production baseline. Full timing, utilization, power, DRC, methodology, CDC, and route reports are available on the remote Vivado host. Setup slack is +0.156 ns (tighter than Build 20's +0.426 ns due to Gap 2 register map additions, but comfortable and better than the intermediate Gap 2 build at +0.078 ns). Hold slack improved to +0.064 ns. DSP count dropped from 140 to 139 via barrel-shift twiddle optimization.</p>
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<p class="muted">Build 20 (v0.1.3-build20) retained as prior reference. Build 19 failed timing (WNS -0.011 ns) due to conflicting XDC generated clock, root-caused and fixed in Build 20.</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<section class="card" style="margin-top:0.8rem;">
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<h2>Report Currency Notice</h2>
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<ul>
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<li>The current routed production-target baseline is <strong>Build 20 (v0.1.3-build20)</strong> with all timing constraints met and 7x setup slack improvement over Build 18.</li>
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<li>The current routed production-target baseline is <strong>Build 21 (v0.1.4-build21)</strong> with all timing constraints met. WNS +0.156 ns, WHS +0.064 ns, 139 DSP48E1, 0.732 W.</li>
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<li>Architectural gaps 2 (GUI Settings), 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR) and 6 (CDC-15) remain for post-bring-up.</li>
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<li>FPGA regression: 19/19 pass (includes new E2E integration test). MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).</li>
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<li>FFT engine optimized: 4-cycle butterfly (20% throughput gain) + barrel-shift twiddle index (frees 1 DSP48). Pending Vivado build verification.</li>
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<li>Detailed Build 20 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build20/</code>.</li>
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<li>FFT engine optimized and Vivado-verified in Build 21: 4-cycle butterfly (20% throughput gain) + barrel-shift twiddle index (freed 1 DSP48, 140 → 139).</li>
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<li>Detailed Build 21 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build21/</code>.</li>
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<li>The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.</li>
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</ul>
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</section>
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