From 15a9cde27439ed5eecf1567a7c9e9d3f6c0091fc Mon Sep 17 00:00:00 2001
From: Jason <83615043+JJassonn69@users.noreply.github.com>
Date: Thu, 16 Apr 2026 11:07:56 +0545
Subject: [PATCH] review(cosim): fix stale comment and wrong docstring
 derivation

golden_reference.py: update comment from 'Simplified' to 'Exact' to
match shaun0927's corrected formula.

fpga_model.py: fix adc_to_signed docstring that incorrectly derived
0x7F80 instead of 0xFF00. Verilog '/' binds tighter than '-', so
{1'b0,8'hFF,9'b0}/2 = 0x1FE00/2 = 0xFF00, not 0xFF<<8 = 0x7F80.
---
 9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py               | 9 ++++++---
 .../9_2_FPGA/tb/cosim/real_data/golden_reference.py      | 2 +-
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py b/9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py
index b412e10..44087d1 100644
--- a/9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py
+++ b/9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py
@@ -291,9 +291,12 @@ class Mixer:
         Convert 8-bit unsigned ADC to 18-bit signed.
         RTL: adc_signed_w = {1'b0, adc_data, {9{1'b0}}} -
                             {1'b0, {8{1'b1}}, {9{1'b0}}} / 2
-        = (adc_data << 9) - (0xFF << 9) / 2
-        = (adc_data << 9) - (0xFF << 8)  [integer division]
-        = (adc_data << 9) - 0x7F80
+
+        Verilog '/' binds tighter than '-', so the division applies
+        only to the second concatenation:
+            {1'b0, 8'hFF, 9'b0} = 0x1FE00
+            0x1FE00 / 2 = 0xFF00 = 65280
+        Result: (adc_data << 9) - 0xFF00
         """
         adc_data_8bit = adc_data_8bit & 0xFF
         # {1'b0, adc_data, 9'b0} = adc_data << 9, zero-padded to 18 bits
diff --git a/9_Firmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py b/9_Firmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py
index c384fe6..6701777 100644
--- a/9_Firmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py
+++ b/9_Firmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py
@@ -290,7 +290,7 @@ def run_ddc(adc_samples):
     for n in range(n_samples):
         # ADC sign conversion: RTL does offset binary → signed 18-bit
         # adc_signed_w = {1'b0, adc_data, 9'b0} - {1'b0, 8'hFF, 9'b0}/2
-        # Simplified: center around zero, scale to 18-bit
+        # Exact: (adc_val << 9) - 0xFF00, where 0xFF00 = {1'b0,8'hFF,9'b0}/2
         adc_val = int(adc_samples[n])
         adc_signed = (adc_val << 9) - 0xFF00  # Exact RTL: {1'b0,adc,9'b0} - {1'b0,8'hFF,9'b0}/2
         adc_signed = saturate(adc_signed, 18)