Convert async→sync reset on DSP/BRAM datapath registers for timing closure

P1-CRITICAL: doppler_processor.v — split FSM into control (async reset)
and BRAM/DSP datapath (sync reset) blocks. Fixes REQP-1839/1840 BRAM
address register corruption risk; enables DSP48 absorption of window
multipliers (mult_i/q).

P1-CRITICAL: frequency_matched_filter.v — convert all 4 pipeline stages
(input capture, multiply, add, saturate) from async to sync reset.
Enables DSP48E1 absorption of complex multiplier registers.

P1-HIGH: fir_lowpass.v — convert adder tree (L0-L4), output stage, and
valid pipeline from async to sync reset. Fixes 856 DPOR-1 warnings
(428 per FIR instance × 2 I/Q channels), enabling DSP48 absorption
of the entire pipelined adder tree.

Expected impact: eliminate ~1000 DRC warnings, improve WNS from +0.019ns
by enabling Vivado to absorb hundreds of registers into DSP48E1/BRAM
hard blocks. Full regression: 13/13 test suites pass (257+ assertions).

9_Firmware/9_2_FPGA/fir_lowpass.v

@@ -109,8 +109,9 @@ end
 // ============================================================================
 // Pipeline Stage 1 (Level 0): Register 16 pairwise sums of 32 multiply results
 // Each addition is a single 36-bit add — one DSP48E1 hop (~1.7ns), fits 10ns.
+// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
 // ============================================================================
-always @(posedge clk or negedge reset_n) begin
+always @(posedge clk) begin
     if (!reset_n) begin
         for (i = 0; i < 16; i = i + 1) begin
             add_l0[i] <= 0;
@@ -128,8 +129,9 @@ end
 
 // ============================================================================
 // Pipeline Stage 2 (Level 1): 8 pairwise sums of 16 Level-0 results
+// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
 // ============================================================================
-always @(posedge clk or negedge reset_n) begin
+always @(posedge clk) begin
     if (!reset_n) begin
         for (i = 0; i < 8; i = i + 1) begin
             add_l1[i] <= 0;
@@ -143,8 +145,9 @@ end
 
 // ============================================================================
 // Pipeline Stage 3 (Level 2): 4 pairwise sums of 8 Level-1 results
+// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
 // ============================================================================
-always @(posedge clk or negedge reset_n) begin
+always @(posedge clk) begin
     if (!reset_n) begin
         for (i = 0; i < 4; i = i + 1) begin
             add_l2[i] <= 0;
@@ -158,8 +161,9 @@ end
 
 // ============================================================================
 // Pipeline Stage 4 (Level 3): 2 pairwise sums of 4 Level-2 results
+// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
 // ============================================================================
-always @(posedge clk or negedge reset_n) begin
+always @(posedge clk) begin
     if (!reset_n) begin
         add_l3[0] <= 0;
         add_l3[1] <= 0;
@@ -171,8 +175,9 @@ end
 
 // ============================================================================
 // Pipeline Stage 5 (Level 4): Final sum of 2 Level-3 results
+// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
 // ============================================================================
-always @(posedge clk or negedge reset_n) begin
+always @(posedge clk) begin
     if (!reset_n) begin
         accumulator_reg <= 0;
     end else if (valid_pipe[4]) begin
@@ -182,8 +187,9 @@ end
 
 // ============================================================================
 // Pipeline Stage 6: Output saturation/rounding (registered)
+// Sync reset enables DSP48E1 absorption (fixes DPOR-1 warnings)
 // ============================================================================
-always @(posedge clk or negedge reset_n) begin
+always @(posedge clk) begin
     if (!reset_n) begin
         data_out <= 0;
         data_out_valid <= 0;
@@ -206,8 +212,9 @@ end
 
 // ============================================================================
 // Valid pipeline shift register
+// Sync reset — no DSP48 involvement but keeps reset style consistent with datapath
 // ============================================================================
-always @(posedge clk or negedge reset_n) begin
+always @(posedge clk) begin
     if (!reset_n) begin
         valid_pipe <= 7'b0000000;
     end else begin