Fix ILA probe insertion script: deferred core creation, exact-path net resolution, Vivado 2025.2 MU_CNT minimum
This commit is contained in:
Jason
@@ -14,10 +14,15 @@
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# 3. Runs full implementation with Build 13 directives
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# 4. Generates bitstream, reports, and .ltx probe file
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#
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# ILA 0: ADC Capture — 400 MHz (rx_inst/clk_400m) — 9 bits
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# ILA 1: DDC Output — 100 MHz (clk_100m_buf) — 37 bits
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# ILA 2: Matched Filter Out — 100 MHz (clk_100m_buf) — 35 bits
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# ILA 3: Doppler Output — 100 MHz (clk_100m_buf) — 45 bits
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# ILA 0: ADC Capture — 400 MHz (rx_inst/adc/clk_400m) — up to 9 bits
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# ILA 1: DDC Output — 100 MHz — up to 37 bits
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# ILA 2: Matched Filter Ctrl — 100 MHz — 4 signals
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# ILA 3: Doppler Output — 100 MHz — up to 45 bits
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#
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# APPROACH: Uses get_nets with -hierarchical wildcards and get_nets -of
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# [get_pins ...] to resolve post-synthesis net names. All probe connections
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# are fault-tolerant — if a net cannot be found it is logged and skipped,
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# rather than aborting the build.
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#
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# Author: auto-generated for Jason Stone
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# Date: 2026-03-18
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@@ -28,7 +33,7 @@
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# ==============================================================================
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set project_base "/home/jason-stone/PLFM_RADAR_work/vivado_project"
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set synth_dcp "${project_base}/aeris10_radar.runs/impl_1/radar_system_top.dcp"
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set synth_dcp "${project_base}/aeris10_radar.runs/synth_1/radar_system_top.dcp"
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set synth_xdc "${project_base}/synth_only.xdc"
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set output_dir "${project_base}/aeris10_radar.runs/impl_ila"
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set top_module "radar_system_top"
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@@ -42,68 +47,130 @@ set run_tag "build13_ila_${timestamp}"
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set ila_depth 4096
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set trigger_pos 512 ;# 512 pre-trigger samples
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# Global counter: total probes actually connected (for final summary)
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set total_probes_connected 0
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# ==============================================================================
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# 1. Helper procedures
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# 1. Helper procedures — fault-tolerant net resolution
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# ==============================================================================
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# Resolve a net with fallback wildcard patterns. Returns the net object or
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# raises an error with diagnostic info if nothing is found.
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proc resolve_net {primary_pattern args} {
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# Try the primary pattern first
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set nets [get_nets -quiet $primary_pattern]
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if {[llength $nets] > 0} {
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puts "INFO: Resolved net '$primary_pattern' -> [lindex $nets 0]"
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return [lindex $nets 0]
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# Try a sequence of strategies to find a single net. Returns the net object
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# or empty string "" if nothing was found. Never errors out.
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#
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# Each element in $strategies is itself a list:
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# { method arg }
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# where method is one of:
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# "net" — try exact path first (get_nets -quiet $arg), then hierarchical
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# "pin" — call get_nets -quiet -of [get_pins -quiet $arg]
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#
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# Example:
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# find_net { {net rx_inst/adc/adc_valid} {net *adc_valid*} }
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#
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proc find_net {strategies} {
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foreach strategy $strategies {
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set method [lindex $strategy 0]
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set arg [lindex $strategy 1]
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switch $method {
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"net" {
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# Try exact path first (works for fully-qualified hierarchical names)
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set result [get_nets -quiet $arg]
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# Fall back to hierarchical search (works for leaf names and wildcards)
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if {[llength $result] == 0} {
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set result [get_nets -quiet -hierarchical $arg]
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}
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}
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"pin" {
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set pins [get_pins -quiet $arg]
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if {[llength $pins] == 0} {
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# Also try hierarchical pin search
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set pins [get_pins -quiet -hierarchical $arg]
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}
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if {[llength $pins] > 0} {
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set result [get_nets -quiet -of $pins]
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} else {
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set result {}
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}
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}
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default {
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set result {}
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}
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}
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if {[llength $result] > 0} {
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# Return the first matching net
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set chosen [lindex $result 0]
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puts " INFO: Resolved '$arg' ($method) -> $chosen"
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return $chosen
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}
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}
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return ""
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}
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# Try each fallback pattern
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foreach fallback $args {
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set nets [get_nets -quiet $fallback]
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if {[llength $nets] > 0} {
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puts "INFO: Primary '$primary_pattern' not found. Resolved via fallback '$fallback' -> [lindex $nets 0]"
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return [lindex $nets 0]
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# Try a sequence of strategies to find a bus (vector) of nets.
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# Returns a Tcl list of net objects. The list may be shorter than requested
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# if some bits were optimised away.
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#
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# Each element in $strategies is { method pattern } where pattern may contain
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# a literal '*' or a specific glob. The procedure evaluates ALL strategies
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# as a batch and picks the first one that returns >= 1 net.
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#
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proc find_bus {strategies} {
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foreach strategy $strategies {
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set method [lindex $strategy 0]
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set arg [lindex $strategy 1]
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switch $method {
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"net" {
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# Try exact path first (works for fully-qualified hierarchical paths)
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set result [get_nets -quiet $arg]
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# Fall back to hierarchical search (leaf names, wildcards)
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if {[llength $result] == 0} {
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set result [get_nets -quiet -hierarchical $arg]
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}
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}
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"pin" {
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set pins [get_pins -quiet $arg]
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if {[llength $pins] == 0} {
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# Also try hierarchical pin search
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set pins [get_pins -quiet -hierarchical $arg]
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}
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if {[llength $pins] > 0} {
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set result [get_nets -quiet -of $pins]
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} else {
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set result {}
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}
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}
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default {
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set result {}
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}
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}
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if {[llength $result] > 0} {
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puts " INFO: Bus resolved via '$arg' ($method) -> [llength $result] nets"
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return $result
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}
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}
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return {}
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}
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# Nothing found — dump available nets in the hierarchy for diagnostics
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set hier_prefix [lindex [split $primary_pattern "/"] 0]
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puts "ERROR: Could not resolve net '$primary_pattern'"
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puts " Available nets under '${hier_prefix}/*' (first 40):"
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set nearby [get_nets -quiet -hierarchical "${hier_prefix}/*"]
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set count 0
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foreach n $nearby {
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puts " $n"
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incr count
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if {$count >= 40} { puts " ... (truncated)"; break }
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}
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error "Net resolution failed for '$primary_pattern'. See log above for nearby nets."
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}
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# Resolve a bus (vector) of nets. Returns a list of net objects.
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# pattern should contain %d which will be replaced with bit indices.
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# Example: resolve_bus "rx_inst/adc/adc_data_cmos\[%d\]" 7 0
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# tries bits 7 down to 0
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proc resolve_bus {pattern msb lsb args} {
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set net_list {}
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for {set i $msb} {$i >= $lsb} {incr i -1} {
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set bit_pattern [string map [list "%d" $i] $pattern]
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# Build fallback list for this bit
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set bit_fallbacks {}
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foreach fb $args {
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lappend bit_fallbacks [string map [list "%d" $i] $fb]
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}
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lappend net_list [resolve_net $bit_pattern {*}$bit_fallbacks]
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}
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return $net_list
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}
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# Connect a list of nets to an ILA probe port, creating additional probe ports
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# as needed. The first probe port (DATA) is already created by create_debug_core.
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# probe_index: starting probe port index (0 = use existing PROBE0)
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# Connect a list of nets to the next available probe port on an ILA core.
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# If the net list is empty, logs a warning and returns the same probe index
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# (no probe port is consumed).
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#
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# ila_name: e.g. u_ila_0
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# probe_index: current probe port index (0 for PROBE0, etc.)
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# net_list: Tcl list of net objects to connect
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# label: human-readable description for log messages
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#
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# Returns the next available probe index.
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proc connect_probe_nets {ila_name probe_index net_list probe_label} {
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#
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proc connect_probe {ila_name probe_index net_list label} {
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global total_probes_connected
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set width [llength $net_list]
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puts "INFO: Connecting $width nets to ${ila_name}/probe${probe_index} ($probe_label)"
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if {$width == 0} {
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puts " WARNING: No nets found for '$label' — skipping probe${probe_index} on $ila_name"
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return $probe_index
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}
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puts " INFO: Connecting $width nets to ${ila_name}/probe${probe_index} ($label)"
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if {$probe_index > 0} {
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create_debug_port $ila_name probe
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@@ -112,9 +179,68 @@ proc connect_probe_nets {ila_name probe_index net_list probe_label} {
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set_property port_width $width [get_debug_ports ${ila_name}/probe${probe_index}]
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connect_debug_port ${ila_name}/probe${probe_index} $net_list
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incr total_probes_connected $width
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return [expr {$probe_index + 1}]
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}
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# Deferred ILA creation — create the debug core, set properties, connect clock,
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# and wire up all resolved probes in one shot. If no probes resolved, the ILA
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# is NOT created at all (avoids dangling probe0 error).
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#
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# ila_name: e.g. u_ila_0
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# clk_net: clock net object
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# probe_list: list of {label net_list} pairs (pre-resolved)
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# depth: ILA sample depth
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#
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# Returns the number of probe ports actually connected.
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#
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proc create_ila_deferred {ila_name clk_net probe_list depth} {
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global total_probes_connected
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# Filter to only probes that have at least 1 net
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set valid_probes {}
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foreach probe_entry $probe_list {
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set label [lindex $probe_entry 0]
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set net_list [lindex $probe_entry 1]
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if {[llength $net_list] > 0} {
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lappend valid_probes [list $label $net_list]
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} else {
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puts " WARNING: No nets found for '$label' on $ila_name — skipping"
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}
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}
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if {[llength $valid_probes] == 0} {
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puts " WARNING: ALL probes failed for $ila_name — ILA core NOT created (avoiding dangling probe0)"
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return 0
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}
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# Now create the debug core — we know we have at least 1 probe
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puts " INFO: Creating $ila_name with [llength $valid_probes] probe(s)"
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create_debug_core $ila_name ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores $ila_name]
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set_property ALL_PROBE_SAME_MU_CNT 2 [get_debug_cores $ila_name]
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set_property C_ADV_TRIGGER false [get_debug_cores $ila_name]
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set_property C_DATA_DEPTH $depth [get_debug_cores $ila_name]
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set_property C_EN_STRG_QUAL true [get_debug_cores $ila_name]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores $ila_name]
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set_property C_TRIGIN_EN false [get_debug_cores $ila_name]
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set_property C_TRIGOUT_EN false [get_debug_cores $ila_name]
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# Connect the clock
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set_property port_width 1 [get_debug_ports ${ila_name}/clk]
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connect_debug_port ${ila_name}/clk [get_nets $clk_net]
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# Connect each resolved probe
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set probe_idx 0
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foreach probe_entry $valid_probes {
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set label [lindex $probe_entry 0]
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set net_list [lindex $probe_entry 1]
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set probe_idx [connect_probe $ila_name $probe_idx $net_list $label]
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}
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return $probe_idx
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}
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# ==============================================================================
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# 2. Open the synthesized checkpoint
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# ==============================================================================
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@@ -142,257 +268,300 @@ puts "INFO: Reading XDC: $synth_xdc"
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read_xdc $synth_xdc
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# ==============================================================================
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# 3. Verify clock nets exist before inserting ILA cores
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# 3. Resolve clock nets
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# ==============================================================================
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puts "\n--- Verifying clock nets ---"
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# 400 MHz clock — BUFG output inside ADC interface
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set clk_400m_net [resolve_net \
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"rx_inst/clk_400m" \
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"rx_inst/adc/clk_400m" \
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"rx_inst/ad9484_interface_400m_inst/clk_400m" \
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"rx_inst/*/O" \
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]
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# 100 MHz system clock — BUFG output
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set clk_100m_net [resolve_net \
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"clk_100m_buf" \
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"bufg_100m/O" \
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"clk_100m_BUFG" \
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]
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puts "\n--- Resolving clock nets ---"
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# 400 MHz clock — inside ADC interface (confirmed resolved to rx_inst/clk_400m)
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set clk_400m_net [find_net {
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{net rx_inst/clk_400m}
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{net rx_inst/adc/clk_400m}
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{net *adc*/clk_400m}
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{net *clk_400m*}
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}]
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if {$clk_400m_net eq ""} {
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error "FATAL: Cannot find 400 MHz clock net. Cannot insert ILA 0."
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}
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puts "INFO: 400 MHz clock net = $clk_400m_net"
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# 100 MHz system clock
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set clk_100m_net [find_net {
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{net clk_100m_IBUF_BUFG}
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{net clk_100m_buf}
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{net clk_100m_BUFG}
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{net *clk_100m*}
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}]
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if {$clk_100m_net eq ""} {
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error "FATAL: Cannot find 100 MHz clock net. Cannot insert ILA 1/2/3."
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}
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puts "INFO: 100 MHz clock net = $clk_100m_net"
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# ==============================================================================
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# 4. ILA 0 — ADC Capture (400 MHz domain)
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#
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# Monitors raw ADC data at the CMOS interface output.
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# 8-bit ADC data + 1-bit valid = 9 probed bits.
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# 4096 samples at 400 MHz => ~10.24 us capture window —
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# sufficient for one chirp segment observation.
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# Probes: ADC data [7:0] + ADC valid = up to 9 bits.
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# 4096 samples at 400 MHz => ~10.24 us capture window.
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#
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# Uses DEFERRED creation: probes are resolved first, ILA is only created
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# if at least one probe has nets. This avoids dangling probe0 errors.
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# ==============================================================================
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puts "\n====== ILA 0: ADC Capture (400 MHz) ======"
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create_debug_core u_ila_0 ila
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
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set_property C_DATA_DEPTH $ila_depth [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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# Probe 0: ADC data [7:0]
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# Post-synth register name is adc_data_400m_reg_reg (double "reg" from synthesis).
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# Bit 7 is inverted: adc_data_400m_reg_reg[7]_inv.
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# Use pin-based discovery which catches both normal and _inv variants.
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set adc_data_nets [find_bus {
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{pin rx_inst/adc/adc_data_400m_reg_reg[*]/Q}
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{net rx_inst/adc/adc_data_400m_reg_reg[*]}
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{pin rx_inst/adc/adc_data_400m_reg[*]/Q}
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{net rx_inst/adc/A[*]}
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{pin rx_inst/adc/adc_data_cmos_reg[*]/Q}
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{net rx_inst/adc/adc_data_400m[*]}
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{net rx_inst/adc/adc_data_cmos[*]}
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}]
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# Clock: 400 MHz BUFG output from ADC interface
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set_property port_width 1 [get_debug_ports u_ila_0/clk]
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connect_debug_port u_ila_0/clk [get_nets $clk_400m_net]
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# Probe 1: ADC valid
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# Net confirmed as rx_inst/adc/adc_valid
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# Pin confirmed as rx_inst/adc/adc_data_valid_400m_reg_reg/Q (double "reg")
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set adc_valid_net [find_net {
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{net rx_inst/adc/adc_valid}
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{pin rx_inst/adc/adc_data_valid_400m_reg_reg/Q}
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{pin rx_inst/adc/adc_valid_reg/Q}
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{net *adc/adc_valid*}
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}]
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if {$adc_valid_net ne ""} {
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set adc_valid_list [list $adc_valid_net]
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} else {
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set adc_valid_list {}
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}
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# Probe 0: adc_data_cmos[7:0] — raw 8-bit ADC sample from AD9484
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set adc_data_nets [resolve_bus \
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"rx_inst/adc/adc_data_cmos\[%d\]" 7 0 \
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"rx_inst/adc/adc_data_400m\[%d\]" \
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"rx_inst/ad9484_interface_400m_inst/adc_data_cmos\[%d\]" \
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"rx_inst/*/adc_data_cmos\[%d\]" \
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# Deferred creation: only create ILA if at least 1 probe resolves
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set ila0_probes [list \
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[list "ADC data" $adc_data_nets] \
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[list "ADC valid" $adc_valid_list] \
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]
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set probe_idx 0
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set probe_idx [connect_probe_nets u_ila_0 $probe_idx $adc_data_nets "ADC raw data\[7:0\]"]
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# Probe 1: adc_valid — data valid strobe
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set adc_valid_net [resolve_net \
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"rx_inst/adc/adc_valid" \
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"rx_inst/ad9484_interface_400m_inst/adc_valid" \
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"rx_inst/*/adc_valid" \
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]
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set probe_idx [connect_probe_nets u_ila_0 $probe_idx [list $adc_valid_net] "ADC valid"]
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puts "INFO: ILA 0 configured — 9 probe bits on 400 MHz clock"
|
||||
set ila0_count [create_ila_deferred u_ila_0 $clk_400m_net $ila0_probes $ila_depth]
|
||||
puts "INFO: ILA 0 — $ila0_count probe ports on 400 MHz clock"
|
||||
|
||||
# ==============================================================================
|
||||
# 5. ILA 1 — DDC Output (100 MHz domain)
|
||||
#
|
||||
# Monitors the digital down-converter output after CIC+FIR decimation.
|
||||
# 18-bit I + 18-bit Q + 1-bit valid = 37 probed bits.
|
||||
# With 4x decimation the effective sample rate is 25 MSPS,
|
||||
# so 4096 samples => ~163.8 us — covers multiple chirp periods.
|
||||
# Probes: DDC I [17:1] + DDC Q [17:1] + DDC valid = up to 35 bits.
|
||||
# Bit 0 is optimized away in synthesis.
|
||||
#
|
||||
# Uses DEFERRED creation to avoid dangling probe0 errors.
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n====== ILA 1: DDC Output (100 MHz) ======"
|
||||
|
||||
create_debug_core u_ila_1 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_1]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_1]
|
||||
set_property C_DATA_DEPTH $ila_depth [get_debug_cores u_ila_1]
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
|
||||
# Probe 0: ddc_out_i — DDC I-channel baseband output
|
||||
# Nets confirmed as rx_inst/ddc/ddc_out_i[1] through [17] (bit 0 optimized away)
|
||||
# Use exact path WITHOUT -hierarchical, then fall back to pin-based and hierarchical
|
||||
set ddc_i_nets [find_bus {
|
||||
{net rx_inst/ddc/ddc_out_i[*]}
|
||||
{pin rx_inst/ddc/ddc_out_i_reg[*]/Q}
|
||||
{net *ddc/ddc_out_i[*]}
|
||||
}]
|
||||
|
||||
# Clock: 100 MHz system clock
|
||||
set_property port_width 1 [get_debug_ports u_ila_1/clk]
|
||||
connect_debug_port u_ila_1/clk [get_nets $clk_100m_net]
|
||||
# Probe 1: ddc_out_q — DDC Q-channel baseband output
|
||||
# Nets confirmed as rx_inst/ddc/ddc_out_q[1] through [17] (bit 0 optimized away)
|
||||
set ddc_q_nets [find_bus {
|
||||
{net rx_inst/ddc/ddc_out_q[*]}
|
||||
{pin rx_inst/ddc/ddc_out_q_reg[*]/Q}
|
||||
{net *ddc/ddc_out_q[*]}
|
||||
}]
|
||||
|
||||
# Probe 0: ddc_out_i[17:0] — DDC I-channel baseband output
|
||||
set ddc_i_nets [resolve_bus \
|
||||
"rx_inst/ddc_out_i\[%d\]" 17 0 \
|
||||
"rx_inst/ddc_400m_inst/ddc_out_i\[%d\]" \
|
||||
"rx_inst/*/ddc_out_i\[%d\]" \
|
||||
# Probe 2: DDC output valid
|
||||
# Confirmed nets: rx_inst/ddc_valid_q, rx_inst/ddc/baseband_valid_q
|
||||
set ddc_valid_net [find_net {
|
||||
{net rx_inst/ddc_valid_q}
|
||||
{net rx_inst/ddc/baseband_valid_q}
|
||||
{net rx_inst/ddc/fir_valid}
|
||||
{pin rx_inst/ddc/baseband_valid_q_reg/Q}
|
||||
{net *ddc*valid*}
|
||||
}]
|
||||
if {$ddc_valid_net ne ""} {
|
||||
set ddc_valid_list [list $ddc_valid_net]
|
||||
} else {
|
||||
set ddc_valid_list {}
|
||||
}
|
||||
|
||||
# Deferred creation: only create ILA if at least 1 probe resolves
|
||||
set ila1_probes [list \
|
||||
[list "DDC I" $ddc_i_nets] \
|
||||
[list "DDC Q" $ddc_q_nets] \
|
||||
[list "DDC valid" $ddc_valid_list] \
|
||||
]
|
||||
set probe_idx 0
|
||||
set probe_idx [connect_probe_nets u_ila_1 $probe_idx $ddc_i_nets "DDC I\[17:0\]"]
|
||||
|
||||
# Probe 1: ddc_out_q[17:0] — DDC Q-channel baseband output
|
||||
set ddc_q_nets [resolve_bus \
|
||||
"rx_inst/ddc_out_q\[%d\]" 17 0 \
|
||||
"rx_inst/ddc_400m_inst/ddc_out_q\[%d\]" \
|
||||
"rx_inst/*/ddc_out_q\[%d\]" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_1 $probe_idx $ddc_q_nets "DDC Q\[17:0\]"]
|
||||
|
||||
# Probe 2: ddc_valid_i — DDC output valid strobe (I path; Q valid assumed coincident)
|
||||
set ddc_valid_net [resolve_net \
|
||||
"rx_inst/ddc_valid_i" \
|
||||
"rx_inst/ddc_400m_inst/ddc_valid_i" \
|
||||
"rx_inst/*/ddc_valid_i" \
|
||||
"rx_inst/ddc_valid" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_1 $probe_idx [list $ddc_valid_net] "DDC valid"]
|
||||
|
||||
puts "INFO: ILA 1 configured — 37 probe bits on 100 MHz clock"
|
||||
set ila1_count [create_ila_deferred u_ila_1 $clk_100m_net $ila1_probes $ila_depth]
|
||||
puts "INFO: ILA 1 — $ila1_count probe ports on 100 MHz clock"
|
||||
|
||||
# ==============================================================================
|
||||
# 6. ILA 2 — Matched Filter Output (100 MHz domain)
|
||||
# 6. ILA 2 — Matched Filter Control (100 MHz domain)
|
||||
#
|
||||
# Monitors the pulse-compression matched filter output.
|
||||
# 16-bit I + 16-bit Q + 1-bit valid + 2-bit segment index = 35 probed bits.
|
||||
# This allows verifying correct chirp segment correlation and range profile.
|
||||
# Reduced probe set: only control/status signals that are confirmed to exist
|
||||
# in the post-synthesis netlist. Data nets (pc_i_w, pc_q_w) do NOT exist
|
||||
# post-synth due to hierarchy flattening.
|
||||
#
|
||||
# Probes: range_profile_valid + mf_valid_out + segment_request[1:0] = 4 bits.
|
||||
#
|
||||
# Uses DEFERRED creation to avoid dangling probe0 errors.
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n====== ILA 2: Matched Filter Output (100 MHz) ======"
|
||||
puts "\n====== ILA 2: Matched Filter Control (100 MHz) ======"
|
||||
|
||||
create_debug_core u_ila_2 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_2]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_2]
|
||||
set_property C_DATA_DEPTH $ila_depth [get_debug_cores u_ila_2]
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_2]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
|
||||
# Probe 0: range_profile_valid
|
||||
# Confirmed nets: rx_inst/mf_dual/range_profile_valid,
|
||||
# rx_inst/mf_dual/m_f_p_c/range_profile_valid,
|
||||
# rx_inst/range_decim/range_profile_valid
|
||||
set rpv_net [find_net {
|
||||
{net rx_inst/mf_dual/range_profile_valid}
|
||||
{net rx_inst/mf_dual/m_f_p_c/range_profile_valid}
|
||||
{net rx_inst/range_decim/range_profile_valid}
|
||||
{pin rx_inst/mf_dual/range_profile_valid_reg/Q}
|
||||
{net *mf_dual/range_profile_valid*}
|
||||
}]
|
||||
if {$rpv_net ne ""} {
|
||||
set rpv_list [list $rpv_net]
|
||||
} else {
|
||||
set rpv_list {}
|
||||
}
|
||||
|
||||
# Clock: 100 MHz system clock (shared with ILA 1)
|
||||
set_property port_width 1 [get_debug_ports u_ila_2/clk]
|
||||
connect_debug_port u_ila_2/clk [get_nets $clk_100m_net]
|
||||
# Probe 1: mf_valid_out (internal MF output valid)
|
||||
# Confirmed nets: rx_inst/mf_dual/m_f_p_c/mf_inst/mf_valid_out,
|
||||
# rx_inst/mf_dual/m_f_p_c/mf_valid_in
|
||||
set mfv_net [find_net {
|
||||
{net rx_inst/mf_dual/m_f_p_c/mf_inst/mf_valid_out}
|
||||
{net rx_inst/mf_dual/m_f_p_c/mf_valid_in}
|
||||
{pin rx_inst/mf_dual/m_f_p_c/mf_inst/mf_valid_out_reg/Q}
|
||||
{net *mf_inst/mf_valid_out*}
|
||||
}]
|
||||
if {$mfv_net ne ""} {
|
||||
set mfv_list [list $mfv_net]
|
||||
} else {
|
||||
set mfv_list {}
|
||||
}
|
||||
|
||||
# Probe 0: pc_i_w[15:0] — matched filter range-compressed I output
|
||||
set mf_i_nets [resolve_bus \
|
||||
"rx_inst/mf_dual/pc_i_w\[%d\]" 15 0 \
|
||||
"rx_inst/matched_filter_multi_segment_inst/pc_i_w\[%d\]" \
|
||||
"rx_inst/*/pc_i_w\[%d\]" \
|
||||
# Probe 2: segment_request[1:0] (confirmed in net dump)
|
||||
set seg_nets [find_bus {
|
||||
{pin rx_inst/mf_dual/segment_request_reg[*]/Q}
|
||||
{net rx_inst/mf_dual/segment_request[*]}
|
||||
{net *mf_dual/segment_request[*]}
|
||||
}]
|
||||
|
||||
# Deferred creation: only create ILA if at least 1 probe resolves
|
||||
set ila2_probes [list \
|
||||
[list "MF range_profile_valid" $rpv_list] \
|
||||
[list "MF mf_valid_out" $mfv_list] \
|
||||
[list "MF segment_request" $seg_nets] \
|
||||
]
|
||||
set probe_idx 0
|
||||
set probe_idx [connect_probe_nets u_ila_2 $probe_idx $mf_i_nets "MF I\[15:0\]"]
|
||||
|
||||
# Probe 1: pc_q_w[15:0] — matched filter range-compressed Q output
|
||||
set mf_q_nets [resolve_bus \
|
||||
"rx_inst/mf_dual/pc_q_w\[%d\]" 15 0 \
|
||||
"rx_inst/matched_filter_multi_segment_inst/pc_q_w\[%d\]" \
|
||||
"rx_inst/*/pc_q_w\[%d\]" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_2 $probe_idx $mf_q_nets "MF Q\[15:0\]"]
|
||||
|
||||
# Probe 2: pc_valid_w — matched filter output valid
|
||||
set mf_valid_net [resolve_net \
|
||||
"rx_inst/mf_dual/pc_valid_w" \
|
||||
"rx_inst/matched_filter_multi_segment_inst/pc_valid_w" \
|
||||
"rx_inst/*/pc_valid_w" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_2 $probe_idx [list $mf_valid_net] "MF valid"]
|
||||
|
||||
# Probe 3: segment_request[1:0] — chirp segment being correlated (0-3)
|
||||
set seg_nets [resolve_bus \
|
||||
"rx_inst/mf_dual/segment_request\[%d\]" 1 0 \
|
||||
"rx_inst/matched_filter_multi_segment_inst/segment_request\[%d\]" \
|
||||
"rx_inst/*/segment_request\[%d\]" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_2 $probe_idx $seg_nets "MF segment\[1:0\]"]
|
||||
|
||||
puts "INFO: ILA 2 configured — 35 probe bits on 100 MHz clock"
|
||||
set ila2_count [create_ila_deferred u_ila_2 $clk_100m_net $ila2_probes $ila_depth]
|
||||
puts "INFO: ILA 2 — $ila2_count probe ports on 100 MHz clock (control signals only)"
|
||||
|
||||
# ==============================================================================
|
||||
# 7. ILA 3 — Doppler Output (100 MHz domain)
|
||||
#
|
||||
# Monitors the Doppler processor output (post-FFT).
|
||||
# 32-bit spectrum + 1-bit valid + 5-bit Doppler bin + 6-bit range bin
|
||||
# + 1-bit frame sync = 45 probed bits.
|
||||
# Allows verification of the range-Doppler map generation.
|
||||
# Probes: doppler_data OBUF [31:0] + doppler_valid + doppler_bin [4:0]
|
||||
# + range_bin [5:0] + new_frame_pulse = up to 45 bits.
|
||||
# Uses _OBUF net variants which are guaranteed to exist at top-level I/O.
|
||||
#
|
||||
# Uses DEFERRED creation to avoid dangling probe0 errors.
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n====== ILA 3: Doppler Output (100 MHz) ======"
|
||||
|
||||
create_debug_core u_ila_3 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_3]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_3]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_3]
|
||||
set_property C_DATA_DEPTH $ila_depth [get_debug_cores u_ila_3]
|
||||
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_3]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_3]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_3]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_3]
|
||||
# Probe 0: Doppler output data [31:0]
|
||||
# Use _OBUF variants (top-level output buffer nets) which are guaranteed
|
||||
# to exist. Fall back to register Q pins if OBUFs are not present.
|
||||
set dop_data_nets [find_bus {
|
||||
{net dbg_doppler_data_OBUF[*]}
|
||||
{pin rx_inst/doppler_proc/doppler_output_reg[*]/Q}
|
||||
{net *doppler_data_OBUF[*]}
|
||||
{net *doppler_output[*]}
|
||||
}]
|
||||
|
||||
# Clock: 100 MHz system clock (shared with ILA 1, ILA 2)
|
||||
set_property port_width 1 [get_debug_ports u_ila_3/clk]
|
||||
connect_debug_port u_ila_3/clk [get_nets $clk_100m_net]
|
||||
# Probe 1: Doppler valid
|
||||
set dop_valid_net [find_net {
|
||||
{net dbg_doppler_valid_OBUF}
|
||||
{net rx_inst/doppler_proc/dbg_doppler_valid_OBUF}
|
||||
{pin rx_inst/doppler_proc/doppler_valid_reg/Q}
|
||||
{net *doppler_valid*}
|
||||
}]
|
||||
if {$dop_valid_net ne ""} {
|
||||
set dop_valid_list [list $dop_valid_net]
|
||||
} else {
|
||||
set dop_valid_list {}
|
||||
}
|
||||
|
||||
# Probe 0: doppler_output[31:0] — Doppler FFT magnitude/spectrum output
|
||||
set dop_out_nets [resolve_bus \
|
||||
"rx_inst/doppler_proc/doppler_output\[%d\]" 31 0 \
|
||||
"rx_inst/doppler_processor_inst/doppler_output\[%d\]" \
|
||||
"rx_inst/*/doppler_output\[%d\]" \
|
||||
# Probe 2: Doppler bin [4:0]
|
||||
set dop_bin_nets [find_bus {
|
||||
{pin rx_inst/doppler_proc/doppler_bin_reg[*]/Q}
|
||||
{net rx_inst/doppler_bin_reg[*]}
|
||||
{net *doppler_bin_OBUF[*]}
|
||||
{net *doppler_bin[*]}
|
||||
}]
|
||||
|
||||
# Probe 3: Range bin [5:0]
|
||||
set rng_bin_nets [find_bus {
|
||||
{pin rx_inst/doppler_proc/range_bin_reg[*]/Q}
|
||||
{net rx_inst/range_bin_reg[*]}
|
||||
{net *range_bin_OBUF[*]}
|
||||
{net *range_bin[*]}
|
||||
}]
|
||||
|
||||
# Probe 4: new_frame_pulse — frame synchronization
|
||||
set frame_net [find_net {
|
||||
{net rx_inst/new_frame_pulse}
|
||||
{net *new_frame_pulse*}
|
||||
{pin rx_inst/new_frame_pulse_reg/Q}
|
||||
{net *frame_pulse*}
|
||||
}]
|
||||
if {$frame_net ne ""} {
|
||||
set frame_list [list $frame_net]
|
||||
} else {
|
||||
set frame_list {}
|
||||
}
|
||||
|
||||
# Deferred creation: only create ILA if at least 1 probe resolves
|
||||
set ila3_probes [list \
|
||||
[list "Doppler data" $dop_data_nets] \
|
||||
[list "Doppler valid" $dop_valid_list] \
|
||||
[list "Doppler bin" $dop_bin_nets] \
|
||||
[list "Range bin" $rng_bin_nets] \
|
||||
[list "Frame sync pulse" $frame_list] \
|
||||
]
|
||||
set probe_idx 0
|
||||
set probe_idx [connect_probe_nets u_ila_3 $probe_idx $dop_out_nets "Doppler spectrum\[31:0\]"]
|
||||
|
||||
# Probe 1: doppler_valid — Doppler output valid strobe
|
||||
set dop_valid_net [resolve_net \
|
||||
"rx_inst/doppler_proc/doppler_valid" \
|
||||
"rx_inst/doppler_processor_inst/doppler_valid" \
|
||||
"rx_inst/*/doppler_valid" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_3 $probe_idx [list $dop_valid_net] "Doppler valid"]
|
||||
|
||||
# Probe 2: doppler_bin[4:0] — Doppler frequency bin index (0-31)
|
||||
set dop_bin_nets [resolve_bus \
|
||||
"rx_inst/doppler_proc/doppler_bin\[%d\]" 4 0 \
|
||||
"rx_inst/doppler_processor_inst/doppler_bin\[%d\]" \
|
||||
"rx_inst/*/doppler_bin\[%d\]" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_3 $probe_idx $dop_bin_nets "Doppler bin\[4:0\]"]
|
||||
|
||||
# Probe 3: range_bin[5:0] — range bin index (0-63)
|
||||
set rng_bin_nets [resolve_bus \
|
||||
"rx_inst/doppler_proc/range_bin\[%d\]" 5 0 \
|
||||
"rx_inst/doppler_processor_inst/range_bin\[%d\]" \
|
||||
"rx_inst/*/range_bin\[%d\]" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_3 $probe_idx $rng_bin_nets "Range bin\[5:0\]"]
|
||||
|
||||
# Probe 4: new_frame_pulse — top-level frame synchronization pulse
|
||||
set frame_net [resolve_net \
|
||||
"rx_inst/new_frame_pulse" \
|
||||
"rx_inst/radar_receiver_final_inst/new_frame_pulse" \
|
||||
"rx_inst/*/new_frame_pulse" \
|
||||
"new_frame_pulse" \
|
||||
]
|
||||
set probe_idx [connect_probe_nets u_ila_3 $probe_idx [list $frame_net] "Frame sync pulse"]
|
||||
|
||||
puts "INFO: ILA 3 configured — 45 probe bits on 100 MHz clock"
|
||||
set ila3_count [create_ila_deferred u_ila_3 $clk_100m_net $ila3_probes $ila_depth]
|
||||
puts "INFO: ILA 3 — $ila3_count probe ports on 100 MHz clock"
|
||||
|
||||
# ==============================================================================
|
||||
# 8. Implement the modified design
|
||||
# 8. Pre-implementation validation
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n--- Pre-implementation ILA summary ---"
|
||||
puts "INFO: Total probe bits connected across all ILAs: $total_probes_connected"
|
||||
|
||||
# Sanity check: make sure we connected SOMETHING
|
||||
if {$total_probes_connected == 0} {
|
||||
error "FATAL: No probe nets were connected to any ILA. Check net names against the post-synth netlist."
|
||||
}
|
||||
|
||||
# List all debug cores for the log
|
||||
set created_cores [get_debug_cores -quiet]
|
||||
if {[llength $created_cores] > 0} {
|
||||
foreach core $created_cores {
|
||||
puts " DEBUG CORE: $core"
|
||||
}
|
||||
} else {
|
||||
puts " WARNING: No debug cores found (this should not happen if total_probes_connected > 0)"
|
||||
}
|
||||
|
||||
# ==============================================================================
|
||||
# 9. Implement the modified design (Build 13 directives)
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n======================================================================"
|
||||
@@ -444,7 +613,7 @@ write_checkpoint -force $final_dcp
|
||||
puts "INFO: Final checkpoint: $final_dcp"
|
||||
|
||||
# ==============================================================================
|
||||
# 9. Generate reports for comparison with Build 13
|
||||
# 10. Generate reports for comparison with Build 13
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n======================================================================"
|
||||
@@ -495,7 +664,7 @@ report_debug_core \
|
||||
puts "INFO: All reports written to $output_dir"
|
||||
|
||||
# ==============================================================================
|
||||
# 10. Write debug probes file (.ltx) for Vivado Hardware Manager
|
||||
# 11. Write debug probes file (.ltx) for Vivado Hardware Manager
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n--- Writing debug probes .ltx file ---"
|
||||
@@ -508,7 +677,7 @@ puts "INFO: Debug probes file: $ltx_file"
|
||||
file copy -force $ltx_file "${output_dir}/debug_nets.ltx"
|
||||
|
||||
# ==============================================================================
|
||||
# 11. Generate bitstream
|
||||
# 12. Generate bitstream
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n======================================================================"
|
||||
@@ -532,7 +701,7 @@ write_cfgmem -force \
|
||||
puts "INFO: SPI flash image: ${output_dir}/${top_module}.bin"
|
||||
|
||||
# ==============================================================================
|
||||
# 12. Final summary
|
||||
# 13. Final summary
|
||||
# ==============================================================================
|
||||
|
||||
puts "\n======================================================================"
|
||||
@@ -545,11 +714,28 @@ puts " Bitstream: $bitstream_file"
|
||||
puts " Debug probes: $ltx_file"
|
||||
puts " Run tag: $run_tag"
|
||||
puts ""
|
||||
puts " ILA Cores Inserted:"
|
||||
puts " u_ila_0 : ADC Capture (400 MHz, 9 bits, depth=$ila_depth)"
|
||||
puts " u_ila_1 : DDC Output (100 MHz, 37 bits, depth=$ila_depth)"
|
||||
puts " u_ila_2 : Matched Filter (100 MHz, 35 bits, depth=$ila_depth)"
|
||||
puts " u_ila_3 : Doppler Output (100 MHz, 45 bits, depth=$ila_depth)"
|
||||
puts " ILA Cores Inserted (only cores with resolved probes):"
|
||||
if {$ila0_count > 0} {
|
||||
puts " u_ila_0 : ADC Capture (400 MHz, depth=$ila_depth, ${ila0_count} probes)"
|
||||
} else {
|
||||
puts " u_ila_0 : ADC Capture — SKIPPED (no probes resolved)"
|
||||
}
|
||||
if {$ila1_count > 0} {
|
||||
puts " u_ila_1 : DDC Output (100 MHz, depth=$ila_depth, ${ila1_count} probes)"
|
||||
} else {
|
||||
puts " u_ila_1 : DDC Output — SKIPPED (no probes resolved)"
|
||||
}
|
||||
if {$ila2_count > 0} {
|
||||
puts " u_ila_2 : MF Control (100 MHz, depth=$ila_depth, ${ila2_count} probes)"
|
||||
} else {
|
||||
puts " u_ila_2 : MF Control — SKIPPED (no probes resolved)"
|
||||
}
|
||||
if {$ila3_count > 0} {
|
||||
puts " u_ila_3 : Doppler Output (100 MHz, depth=$ila_depth, ${ila3_count} probes)"
|
||||
} else {
|
||||
puts " u_ila_3 : Doppler Output — SKIPPED (no probes resolved)"
|
||||
}
|
||||
puts " Total probe bits connected: $total_probes_connected"
|
||||
puts ""
|
||||
puts " Compare these reports against Build 13 baseline:"
|
||||
puts " - timing_summary_final.rpt (WNS/TNS/WHS/THS)"
|
||||
|
||||
Reference in New Issue
Block a user