Add TE0712/TE0701 split target with dedicated top, XDC, and build flow
This commit is contained in:
Jason
@@ -1,18 +1,24 @@
|
||||
# AERIS-10 FPGA Constraint Files
|
||||
|
||||
## Two Targets
|
||||
## Three Targets
|
||||
|
||||
| File | Device | Package | Purpose |
|
||||
|------|--------|---------|---------|
|
||||
| `xc7a50t_ftg256.xdc` | XC7A50T-2FTG256I | FTG256 (256-ball BGA) | Upstream author's board (copy of `cntrt.xdc`) |
|
||||
| `xc7a200t_fbg484.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Production board (new PCB design) |
|
||||
| `te0712_te0701_minimal.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Trenz dev split target (minimal clock/reset + LEDs/status) |
|
||||
|
||||
## Why Two Files
|
||||
## Why Three Files
|
||||
|
||||
The upstream prototype uses a smaller XC7A50T in an FTG256 package. The production
|
||||
AERIS-10 radar migrates to the XC7A200T for more logic, BRAM, and DSP resources.
|
||||
The two devices have completely different packages and pin names, so each needs its
|
||||
own constraint file. Both files constrain the same RTL top module (`radar_system_top.v`).
|
||||
own constraint file.
|
||||
|
||||
The Trenz TE0712/TE0701 path uses the same FPGA part as production but different board
|
||||
pinout and peripherals. The dev target is split into its own top wrapper
|
||||
(`radar_system_top_te0712_dev.v`) and minimal constraints file to avoid accidental mixing
|
||||
of production pin assignments during bring-up.
|
||||
|
||||
## Bank Voltage Assignments
|
||||
|
||||
@@ -49,7 +55,7 @@ own constraint file. Both files constrain the same RTL top module (`radar_system
|
||||
|
||||
## How to Select in Vivado
|
||||
|
||||
In the Vivado project, only one XDC should be active at a time:
|
||||
In the Vivado project, only one target XDC should be active at a time:
|
||||
|
||||
1. Add both files to the project: `File > Add Sources > Add Constraints`
|
||||
2. In the Sources panel, right-click the XDC you do NOT want and select
|
||||
@@ -64,8 +70,58 @@ read_xdc constraints/xc7a200t_fbg484.xdc
|
||||
|
||||
# For upstream target:
|
||||
read_xdc constraints/xc7a50t_ftg256.xdc
|
||||
|
||||
# For Trenz TE0712/TE0701 split target:
|
||||
read_xdc constraints/te0712_te0701_minimal.xdc
|
||||
```
|
||||
|
||||
## Top Modules by Target
|
||||
|
||||
| Target | Top module | Notes |
|
||||
|--------|------------|-------|
|
||||
| Upstream FTG256 | `radar_system_top` | Legacy board support |
|
||||
| Production FBG484 | `radar_system_top` | Main AERIS-10 board |
|
||||
| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | Minimal bring-up wrapper while pinout/peripherals are migrated |
|
||||
|
||||
## Trenz Split Status
|
||||
|
||||
- `constraints/te0712_te0701_minimal.xdc` currently includes verified TE0712 pins:
|
||||
- `clk_100m` -> `R4` (TE0712 `CLK1B[0]`, 50 MHz source)
|
||||
- `reset_n` -> `T3` (TE0712 reset pin)
|
||||
- `user_led` and `system_status` are now mapped to TE0701 FMC LA lines through TE0712 B16
|
||||
package pins (GPIO export path, not TE0701 onboard LED D1..D8).
|
||||
- Temporary `NSTD-1`/`UCIO-1` severity downgrades were removed after pin assignment.
|
||||
|
||||
### Current GPIO Export Map
|
||||
|
||||
| Port | TE0712 package pin | TE0712 net | TE0701 FMC net |
|
||||
|------|---------------------|------------|----------------|
|
||||
| `user_led[0]` | `A19` | `B16_L17_N` | `FMC_LA14_N` |
|
||||
| `user_led[1]` | `A18` | `B16_L17_P` | `FMC_LA14_P` |
|
||||
| `user_led[2]` | `F20` | `B16_L18_N` | `FMC_LA13_N` |
|
||||
| `user_led[3]` | `F19` | `B16_L18_P` | `FMC_LA13_P` |
|
||||
| `system_status[0]` | `F18` | `B16_L15_P` | `FMC_LA5_N` |
|
||||
| `system_status[1]` | `E18` | `B16_L15_N` | `FMC_LA5_P` |
|
||||
| `system_status[2]` | `C22` | `B16_L20_P` | `FMC_LA6_N` |
|
||||
| `system_status[3]` | `B22` | `B16_L20_N` | `FMC_LA6_P` |
|
||||
|
||||
Note: FMC direction/N/P labeling must be validated against TE0701 connector orientation
|
||||
and I/O Planner before final hardware sign-off.
|
||||
|
||||
## Trenz Batch Build
|
||||
|
||||
Use the dedicated script for the split dev target:
|
||||
|
||||
```bash
|
||||
vivado -mode batch -source scripts/build_te0712_dev.tcl
|
||||
```
|
||||
|
||||
Outputs:
|
||||
- Project directory: `vivado_te0712_dev/`
|
||||
- Reports: `vivado_te0712_dev/reports/`
|
||||
- Top module: `radar_system_top_te0712_dev`
|
||||
- Constraint file: `constraints/te0712_te0701_minimal.xdc`
|
||||
|
||||
## Notes
|
||||
|
||||
- The production XDC pin assignments are **recommended** for the new PCB.
|
||||
|
||||
@@ -0,0 +1,62 @@
|
||||
# ============================================================================
|
||||
# AERIS-10 TE0712/TE0701 DEV TARGET (MINIMAL SPLIT)
|
||||
# ============================================================================
|
||||
# Target part: XC7A200T-2FBG484I (TE0712-03-82I36-A)
|
||||
# Board: TE0701-06 carrier
|
||||
#
|
||||
# This XDC is intentionally minimal and is used with:
|
||||
# top = radar_system_top_te0712_dev
|
||||
#
|
||||
# Replace PACKAGE_PIN assignments with the exact TE0701-06 net mapping from
|
||||
# the Trenz schematics/board files before hardware programming.
|
||||
# ============================================================================
|
||||
|
||||
set_property CFGBVS VCCO [current_design]
|
||||
set_property CONFIG_VOLTAGE 3.3 [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
|
||||
|
||||
# Clock/reset IO standards
|
||||
# TE0712 reference design mapping:
|
||||
# CLK1B[0] -> R4 (50 MHz, LVCMOS15)
|
||||
# reset -> T3 (LVCMOS15)
|
||||
# We keep the top-level port name as clk_100m in the dev wrapper for now,
|
||||
# but it is physically sourced from the 50 MHz CLK1B net on TE0712.
|
||||
set_property IOSTANDARD LVCMOS15 [get_ports {clk_100m}]
|
||||
set_property IOSTANDARD LVCMOS15 [get_ports {reset_n}]
|
||||
set_property PULLUP true [get_ports {reset_n}]
|
||||
|
||||
# Status/output IO standards
|
||||
# These outputs are currently exported to TE0701 FMC LA lines (not onboard LEDs).
|
||||
# Assumption: FMC VADJ/VCCIO16 is set for 2.5V signaling.
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {user_led[*]}]
|
||||
set_property IOSTANDARD LVCMOS25 [get_ports {system_status[*]}]
|
||||
|
||||
# Clock constraint
|
||||
create_clock -name clk_100m -period 20.000 [get_ports {clk_100m}]
|
||||
set_input_jitter [get_clocks clk_100m] 0.100
|
||||
|
||||
# --------------------------------------------------------------------------
|
||||
# Known-good TE0712 package pin mapping from official reference design
|
||||
# --------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN R4 [get_ports {clk_100m}]
|
||||
set_property PACKAGE_PIN T3 [get_ports {reset_n}]
|
||||
|
||||
# --------------------------------------------------------------------------
|
||||
# TE0701 FMC export mapping (derived from TE0701 FMC map + TE0712 B16 mapping)
|
||||
# user_led[0..3] -> FMC_LA14_N/P, FMC_LA13_N/P
|
||||
# system_status[] -> FMC_LA5_N/P, FMC_LA6_N/P
|
||||
# --------------------------------------------------------------------------
|
||||
set_property PACKAGE_PIN A19 [get_ports {user_led[0]}]
|
||||
set_property PACKAGE_PIN A18 [get_ports {user_led[1]}]
|
||||
set_property PACKAGE_PIN F20 [get_ports {user_led[2]}]
|
||||
set_property PACKAGE_PIN F19 [get_ports {user_led[3]}]
|
||||
|
||||
set_property PACKAGE_PIN F18 [get_ports {system_status[0]}]
|
||||
set_property PACKAGE_PIN E18 [get_ports {system_status[1]}]
|
||||
set_property PACKAGE_PIN C22 [get_ports {system_status[2]}]
|
||||
set_property PACKAGE_PIN B22 [get_ports {system_status[3]}]
|
||||
|
||||
# --------------------------------------------------------------------------
|
||||
# Keep implementation checks strict.
|
||||
# report_timing_summary -report_unconstrained
|
||||
# report_drc
|
||||
Reference in New Issue
Block a user