Add TE0712/TE0701 split target with dedicated top, XDC, and build flow
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Jason
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# AERIS-10 FPGA Constraint Files
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## Two Targets
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## Three Targets
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| File | Device | Package | Purpose |
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|------|--------|---------|---------|
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| `xc7a50t_ftg256.xdc` | XC7A50T-2FTG256I | FTG256 (256-ball BGA) | Upstream author's board (copy of `cntrt.xdc`) |
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| `xc7a200t_fbg484.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Production board (new PCB design) |
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| `te0712_te0701_minimal.xdc` | XC7A200T-2FBG484I | FBG484 (484-ball BGA) | Trenz dev split target (minimal clock/reset + LEDs/status) |
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## Why Two Files
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## Why Three Files
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The upstream prototype uses a smaller XC7A50T in an FTG256 package. The production
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AERIS-10 radar migrates to the XC7A200T for more logic, BRAM, and DSP resources.
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The two devices have completely different packages and pin names, so each needs its
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own constraint file. Both files constrain the same RTL top module (`radar_system_top.v`).
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own constraint file.
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The Trenz TE0712/TE0701 path uses the same FPGA part as production but different board
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pinout and peripherals. The dev target is split into its own top wrapper
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(`radar_system_top_te0712_dev.v`) and minimal constraints file to avoid accidental mixing
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of production pin assignments during bring-up.
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## Bank Voltage Assignments
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@@ -49,7 +55,7 @@ own constraint file. Both files constrain the same RTL top module (`radar_system
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## How to Select in Vivado
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In the Vivado project, only one XDC should be active at a time:
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In the Vivado project, only one target XDC should be active at a time:
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1. Add both files to the project: `File > Add Sources > Add Constraints`
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2. In the Sources panel, right-click the XDC you do NOT want and select
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@@ -64,8 +70,58 @@ read_xdc constraints/xc7a200t_fbg484.xdc
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# For upstream target:
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read_xdc constraints/xc7a50t_ftg256.xdc
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# For Trenz TE0712/TE0701 split target:
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read_xdc constraints/te0712_te0701_minimal.xdc
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```
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## Top Modules by Target
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| Target | Top module | Notes |
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|--------|------------|-------|
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| Upstream FTG256 | `radar_system_top` | Legacy board support |
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| Production FBG484 | `radar_system_top` | Main AERIS-10 board |
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| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | Minimal bring-up wrapper while pinout/peripherals are migrated |
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## Trenz Split Status
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- `constraints/te0712_te0701_minimal.xdc` currently includes verified TE0712 pins:
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- `clk_100m` -> `R4` (TE0712 `CLK1B[0]`, 50 MHz source)
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- `reset_n` -> `T3` (TE0712 reset pin)
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- `user_led` and `system_status` are now mapped to TE0701 FMC LA lines through TE0712 B16
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package pins (GPIO export path, not TE0701 onboard LED D1..D8).
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- Temporary `NSTD-1`/`UCIO-1` severity downgrades were removed after pin assignment.
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### Current GPIO Export Map
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| Port | TE0712 package pin | TE0712 net | TE0701 FMC net |
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|------|---------------------|------------|----------------|
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| `user_led[0]` | `A19` | `B16_L17_N` | `FMC_LA14_N` |
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| `user_led[1]` | `A18` | `B16_L17_P` | `FMC_LA14_P` |
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| `user_led[2]` | `F20` | `B16_L18_N` | `FMC_LA13_N` |
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| `user_led[3]` | `F19` | `B16_L18_P` | `FMC_LA13_P` |
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| `system_status[0]` | `F18` | `B16_L15_P` | `FMC_LA5_N` |
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| `system_status[1]` | `E18` | `B16_L15_N` | `FMC_LA5_P` |
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| `system_status[2]` | `C22` | `B16_L20_P` | `FMC_LA6_N` |
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| `system_status[3]` | `B22` | `B16_L20_N` | `FMC_LA6_P` |
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Note: FMC direction/N/P labeling must be validated against TE0701 connector orientation
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and I/O Planner before final hardware sign-off.
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## Trenz Batch Build
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Use the dedicated script for the split dev target:
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```bash
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vivado -mode batch -source scripts/build_te0712_dev.tcl
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```
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Outputs:
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- Project directory: `vivado_te0712_dev/`
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- Reports: `vivado_te0712_dev/reports/`
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- Top module: `radar_system_top_te0712_dev`
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- Constraint file: `constraints/te0712_te0701_minimal.xdc`
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## Notes
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- The production XDC pin assignments are **recommended** for the new PCB.
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@@ -0,0 +1,62 @@
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# ============================================================================
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# AERIS-10 TE0712/TE0701 DEV TARGET (MINIMAL SPLIT)
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# ============================================================================
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# Target part: XC7A200T-2FBG484I (TE0712-03-82I36-A)
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# Board: TE0701-06 carrier
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#
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# This XDC is intentionally minimal and is used with:
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# top = radar_system_top_te0712_dev
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#
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# Replace PACKAGE_PIN assignments with the exact TE0701-06 net mapping from
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# the Trenz schematics/board files before hardware programming.
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# ============================================================================
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
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# Clock/reset IO standards
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# TE0712 reference design mapping:
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# CLK1B[0] -> R4 (50 MHz, LVCMOS15)
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# reset -> T3 (LVCMOS15)
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# We keep the top-level port name as clk_100m in the dev wrapper for now,
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# but it is physically sourced from the 50 MHz CLK1B net on TE0712.
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set_property IOSTANDARD LVCMOS15 [get_ports {clk_100m}]
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set_property IOSTANDARD LVCMOS15 [get_ports {reset_n}]
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set_property PULLUP true [get_ports {reset_n}]
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# Status/output IO standards
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# These outputs are currently exported to TE0701 FMC LA lines (not onboard LEDs).
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# Assumption: FMC VADJ/VCCIO16 is set for 2.5V signaling.
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set_property IOSTANDARD LVCMOS25 [get_ports {user_led[*]}]
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set_property IOSTANDARD LVCMOS25 [get_ports {system_status[*]}]
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# Clock constraint
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create_clock -name clk_100m -period 20.000 [get_ports {clk_100m}]
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set_input_jitter [get_clocks clk_100m] 0.100
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# --------------------------------------------------------------------------
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# Known-good TE0712 package pin mapping from official reference design
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# --------------------------------------------------------------------------
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set_property PACKAGE_PIN R4 [get_ports {clk_100m}]
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set_property PACKAGE_PIN T3 [get_ports {reset_n}]
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# --------------------------------------------------------------------------
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# TE0701 FMC export mapping (derived from TE0701 FMC map + TE0712 B16 mapping)
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# user_led[0..3] -> FMC_LA14_N/P, FMC_LA13_N/P
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# system_status[] -> FMC_LA5_N/P, FMC_LA6_N/P
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# --------------------------------------------------------------------------
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set_property PACKAGE_PIN A19 [get_ports {user_led[0]}]
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set_property PACKAGE_PIN A18 [get_ports {user_led[1]}]
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set_property PACKAGE_PIN F20 [get_ports {user_led[2]}]
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set_property PACKAGE_PIN F19 [get_ports {user_led[3]}]
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set_property PACKAGE_PIN F18 [get_ports {system_status[0]}]
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set_property PACKAGE_PIN E18 [get_ports {system_status[1]}]
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set_property PACKAGE_PIN C22 [get_ports {system_status[2]}]
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set_property PACKAGE_PIN B22 [get_ports {system_status[3]}]
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# --------------------------------------------------------------------------
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# Keep implementation checks strict.
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# report_timing_summary -report_unconstrained
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# report_drc
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@@ -0,0 +1,47 @@
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`timescale 1ns / 1ps
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module radar_system_top_te0712_dev (
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input wire clk_100m,
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input wire reset_n,
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output wire [3:0] user_led,
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output wire [3:0] system_status
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);
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wire clk_100m_buf;
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wire sys_reset_n;
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reg [31:0] hb_counter;
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BUFG bufg_100m (
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.I(clk_100m),
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.O(clk_100m_buf)
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);
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(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync;
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always @(posedge clk_100m_buf or negedge reset_n) begin
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if (!reset_n) begin
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reset_sync <= 2'b00;
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end else begin
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reset_sync <= {reset_sync[0], 1'b1};
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end
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end
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assign sys_reset_n = reset_sync[1];
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always @(posedge clk_100m_buf or negedge sys_reset_n) begin
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if (!sys_reset_n) begin
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hb_counter <= 32'd0;
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end else begin
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hb_counter <= hb_counter + 1'b1;
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end
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end
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assign user_led[0] = hb_counter[24];
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assign user_led[1] = hb_counter[25];
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assign user_led[2] = hb_counter[26];
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assign user_led[3] = sys_reset_n;
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assign system_status[0] = sys_reset_n;
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assign system_status[1] = hb_counter[23];
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assign system_status[2] = hb_counter[24];
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assign system_status[3] = hb_counter[25];
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endmodule
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@@ -0,0 +1,60 @@
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# build_te0712_dev.tcl
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#
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# Vivado batch build for Trenz TE0712/TE0701 split target.
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#
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# Usage:
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# vivado -mode batch -source scripts/build_te0712_dev.tcl
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#
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# Notes:
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# - This target uses radar_system_top_te0712_dev.v (minimal bring-up top).
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# - constraints/te0712_te0701_minimal.xdc currently has verified clock/reset
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# pins and placeholder LED/status pins.
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set script_dir [file dirname [file normalize [info script]]]
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set project_root [file normalize [file join $script_dir ".."]]
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set project_name "aeris10_te0712_dev"
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set build_dir [file join $project_root "vivado_te0712_dev"]
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set reports_dir [file join $build_dir "reports"]
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set top_file [file join $project_root "radar_system_top_te0712_dev.v"]
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set xdc_file [file join $project_root "constraints" "te0712_te0701_minimal.xdc"]
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file mkdir $build_dir
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file mkdir $reports_dir
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create_project -force $project_name $build_dir -part xc7a200tfbg484-2
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set_property target_language Verilog [current_project]
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add_files -norecurse $top_file
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add_files -fileset constrs_1 -norecurse $xdc_file
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set_property top radar_system_top_te0712_dev [current_fileset]
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update_compile_order -fileset sources_1
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puts "INFO: Launching implementation to bitstream..."
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launch_runs impl_1 -to_step write_bitstream -jobs 8
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wait_on_run impl_1
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set impl_status [get_property STATUS [get_runs impl_1]]
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puts "INFO: impl_1 status: $impl_status"
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if {![string match "*Complete*" $impl_status]} {
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error "Implementation did not complete successfully. Status: $impl_status"
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}
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open_run impl_1
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report_clocks -file [file join $reports_dir "clocks.rpt"]
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report_clock_interaction -file [file join $reports_dir "clock_interaction.rpt"]
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report_timing_summary -report_unconstrained -max_paths 100 -file [file join $reports_dir "timing_summary.rpt"]
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report_cdc -details -file [file join $reports_dir "cdc.rpt"]
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report_exceptions -file [file join $reports_dir "exceptions.rpt"]
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report_drc -file [file join $reports_dir "drc.rpt"]
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report_utilization -file [file join $reports_dir "utilization.rpt"]
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set bit_file [get_property BITSTREAM.FILE [current_design]]
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puts "INFO: Build complete."
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puts "INFO: Bitstream: $bit_file"
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puts "INFO: Reports: $reports_dir"
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