E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
RTL fixes discovered via new end-to-end testbench: - plfm_chirp_controller: TX/RX mixer enables now mutually exclusive by FSM state (Fix #4), preventing simultaneous TX+RX activation - usb_data_interface: stream control reset default 3'b001 (range-only), added doppler/cfar data_pending sticky flags, write FSM triggers on range_valid only — eliminates startup deadlock (Fix #5) - radar_receiver_final: STM32 toggle signals wired through for mode-00 pass-through, dynamic frame detection via host_chirps_per_elev - radar_system_top: STM32 toggle signal wiring to receiver instance - chirp_memory_loader_param: explicit readmemh range for short chirp Test infrastructure: - New tb_system_e2e.v: 46 checks across 12 groups (reset, TX, safety, RX, USB R/W, CDC, beam scanning, reset recovery, stream control, latency budgets, watchdog) - tb_usb_data_interface: Tests 21/22/56 updated for data_pending architecture (preload flags, verify consumption instead of state) - tb_chirp_controller: mixer tests T7.1/T7.2 updated for Fix #4 - run_regression.sh: PASS/FAIL regex fixed to match only [PASS]/[FAIL] markers, added E2E test entry - Updated rx_final_doppler_out.csv golden data
This commit is contained in:
Jason
@@ -69,9 +69,10 @@ initial begin
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`endif
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// === LOAD SHORT CHIRP ===
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// Load first 50 samples (0-49)
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$readmemh(SHORT_I_FILE, short_chirp_i);
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$readmemh(SHORT_Q_FILE, short_chirp_q);
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// Load first 50 samples (0-49). Explicit range prevents iverilog warning
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// about insufficient words for the full [0:1023] array.
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$readmemh(SHORT_I_FILE, short_chirp_i, 0, 49);
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$readmemh(SHORT_Q_FILE, short_chirp_q, 0, 49);
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`ifdef SIMULATION
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if (DEBUG) $display("[MEM] Loaded short chirp (0-49)");
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`endif
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@@ -80,9 +80,13 @@ assign elevation__toggling = new_elevation;
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assign azimuth__toggling = new_azimuth;
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assign new_chirp_frame = (current_state == IDLE && next_state == LONG_CHIRP);
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// Mixers Enabling
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assign rx_mixer_en = mixers_enable;
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assign tx_mixer_en = mixers_enable;
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// Mixer TX/RX sequencing — mutually exclusive based on chirp FSM state.
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// TX mixer active during chirp transmission, RX mixer during listen.
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// Both require mixers_enable (STM32 master enable) to be high.
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assign tx_mixer_en = mixers_enable && (current_state == LONG_CHIRP ||
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current_state == SHORT_CHIRP);
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assign rx_mixer_en = mixers_enable && (current_state == LONG_LISTEN ||
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current_state == SHORT_LISTEN);
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// ADTR1000 pull to ground tx and rx load pins if not used
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assign adar_tx_load_1 = 1'b0;
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@@ -35,7 +35,15 @@ module radar_receiver_final (
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input wire [15:0] host_guard_cycles,
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input wire [15:0] host_short_chirp_cycles,
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input wire [15:0] host_short_listen_cycles,
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input wire [5:0] host_chirps_per_elev
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input wire [5:0] host_chirps_per_elev,
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// STM32 toggle signals for mode 00 (STM32-driven) pass-through.
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// These are CDC-synchronized in radar_system_top.v / radar_transmitter.v
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// before reaching this module. In mode 00, the RX mode controller uses
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// these to synchronize receiver processing with STM32-timed chirps.
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input wire stm32_new_chirp_rx,
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input wire stm32_new_elevation_rx,
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input wire stm32_new_azimuth_rx
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);
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// ========== INTERNAL SIGNALS ==========
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@@ -95,9 +103,9 @@ radar_mode_controller rmc (
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.clk(clk),
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.reset_n(reset_n),
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.mode(host_mode), // Controlled by host via USB (default: 2'b01 auto-scan)
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.stm32_new_chirp(1'b0), // Unused in auto mode
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.stm32_new_elevation(1'b0), // Unused in auto mode
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.stm32_new_azimuth(1'b0), // Unused in auto mode
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.stm32_new_chirp(stm32_new_chirp_rx),
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.stm32_new_elevation(stm32_new_elevation_rx),
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.stm32_new_azimuth(stm32_new_azimuth_rx),
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.trigger(host_trigger), // Single-chirp trigger from host via USB
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// Gap 2: Runtime-configurable timing from host USB commands
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.cfg_long_chirp_cycles(host_long_chirp_cycles),
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@@ -302,27 +310,17 @@ always @(posedge clk or negedge reset_n) begin
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// Default: no pulse
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new_frame_pulse <= 1'b0;
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// ===== CHOOSE ONE FRAME DETECTION METHOD =====
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// METHOD A: Detect frame start at chirp_counter = 0
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// (Assumes frames are 64 chirps: 0-63)
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//if (chirp_counter == 6'd0 && chirp_counter_prev != 6'd0) begin
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// new_frame_pulse <= 1'b1;
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//end
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// METHOD B: Detect frame start at chirp_counter = 0 AND 32
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// (For 32-chirp frames in a 64-chirp sequence)
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if ((chirp_counter == 6'd0 || chirp_counter == 6'd32) &&
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(chirp_counter_prev != chirp_counter)) begin
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new_frame_pulse <= 1'b1;
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end
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// METHOD C: Programmable frame start
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// localparam FRAME_START_CHIRP = 6'd0; // Set based on your sequence
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// if (chirp_counter == FRAME_START_CHIRP &&
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// chirp_counter_prev != FRAME_START_CHIRP) begin
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// new_frame_pulse <= 1'b1;
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// end
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// Dynamic frame detection using host_chirps_per_elev.
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// Detect frame boundary when chirp_counter changes AND is a
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// multiple of host_chirps_per_elev (0, N, 2N, 3N, ...).
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// Uses a modulo counter that resets at host_chirps_per_elev.
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if (chirp_counter != chirp_counter_prev) begin
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if (chirp_counter == 6'd0 ||
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chirp_counter == host_chirps_per_elev ||
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chirp_counter == {host_chirps_per_elev, 1'b0}) begin
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new_frame_pulse <= 1'b1;
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end
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end
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// Store previous value
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chirp_counter_prev <= chirp_counter;
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@@ -445,7 +445,13 @@ radar_receiver_final rx_inst (
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.host_guard_cycles(host_guard_cycles),
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.host_short_chirp_cycles(host_short_chirp_cycles),
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.host_short_listen_cycles(host_short_listen_cycles),
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.host_chirps_per_elev(host_chirps_per_elev)
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.host_chirps_per_elev(host_chirps_per_elev),
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// STM32 toggle signals for RX mode controller (mode 00 pass-through).
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// These are the raw GPIO inputs — the RX mode controller's edge detectors
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// (inside radar_mode_controller) handle debouncing/edge detection.
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.stm32_new_chirp_rx(stm32_new_chirp),
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.stm32_new_elevation_rx(stm32_new_elevation),
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.stm32_new_azimuth_rx(stm32_new_azimuth)
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);
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// ============================================================================
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@@ -275,8 +275,8 @@ run_test() {
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# Count PASS/FAIL in output (testbenches use explicit [PASS]/[FAIL] markers)
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local test_pass test_fail
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test_pass=$(echo "$output" | grep -ci '\bPASS\b' || true)
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test_fail=$(echo "$output" | grep -ci '\bFAIL\b' || true)
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test_pass=$(echo "$output" | grep -Ec '^\[PASS([^]]*)\]' || true)
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test_fail=$(echo "$output" | grep -Ec '^\[FAIL([^]]*)\]' || true)
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if [[ "$test_fail" -gt 0 ]]; then
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echo -e "${RED}FAIL${NC} (pass=$test_pass, fail=$test_fail)"
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@@ -403,7 +403,7 @@ if [[ "$QUICK" -eq 0 ]]; then
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matched_filter_multi_segment.v matched_filter_processing_chain.v \
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range_bin_decimator.v doppler_processor.v xfft_32.v fft_engine.v
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# Full system top
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# Full system top (monitoring-only, legacy)
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run_test "System Top (radar_system_tb)" \
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tb/tb_system_reg.vvp \
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tb/radar_system_tb.v radar_system_top.v \
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@@ -415,9 +415,22 @@ if [[ "$QUICK" -eq 0 ]]; then
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matched_filter_multi_segment.v matched_filter_processing_chain.v \
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range_bin_decimator.v doppler_processor.v xfft_32.v fft_engine.v \
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usb_data_interface.v edge_detector.v radar_mode_controller.v
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# E2E integration (46 strict checks: TX, RX, USB R/W, CDC, safety, reset)
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run_test "System E2E (tb_system_e2e)" \
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tb/tb_system_e2e_reg.vvp \
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tb/tb_system_e2e.v radar_system_top.v \
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radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
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radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
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ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
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cdc_modules.v fir_lowpass.v ddc_input_interface.v \
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chirp_memory_loader_param.v latency_buffer.v \
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matched_filter_multi_segment.v matched_filter_processing_chain.v \
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range_bin_decimator.v doppler_processor.v xfft_32.v fft_engine.v \
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usb_data_interface.v edge_detector.v radar_mode_controller.v
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else
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echo " (skipped receiver golden + system top — use without --quick)"
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SKIP=$((SKIP + 3))
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echo " (skipped receiver golden + system top + E2E — use without --quick)"
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SKIP=$((SKIP + 4))
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fi
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echo ""
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File diff suppressed because it is too large
Load Diff
@@ -431,13 +431,14 @@ initial begin
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// =====================================================================
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$display("--- Group 7: Mixer Control Outputs ---");
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// T7.1: rx_mixer_en follows mixers_enable
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// T7.1: In IDLE state, both mixers are off even with mixers_enable=1
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// (Fix #4: mixers are state-dependent, not tied to mixers_enable directly)
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mixers_enable = 1;
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#1;
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check("rx_mixer_en follows mixers_enable", rx_mixer_en == 1'b1);
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check("rx_mixer_en off in IDLE (state-dependent)", rx_mixer_en == 1'b0);
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// T7.2: tx_mixer_en follows mixers_enable
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check("tx_mixer_en follows mixers_enable", tx_mixer_en == 1'b1);
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// T7.2: tx_mixer_en also off in IDLE
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check("tx_mixer_en off in IDLE (state-dependent)", tx_mixer_en == 1'b0);
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// T7.3: ADAR load pins tied low
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check("ADAR load pins: adar_tx_load_1 is 0", adar_tx_load_1 == 1'b0);
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File diff suppressed because it is too large
Load Diff
@@ -180,7 +180,10 @@ module tb_usb_data_interface;
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status_chirps_per_elev = 6'd32;
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repeat (6) @(posedge ft601_clk_in);
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reset_n = 1;
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repeat (2) @(posedge ft601_clk_in);
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// Wait enough cycles for stream_control CDC to propagate
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// (DUT resets stream_ctrl_sync to 3'b001; TB sets stream_control=3'b111
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// which needs 2-stage sync + 1 cycle = 4+ ft601_clk cycles)
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repeat (6) @(posedge ft601_clk_in);
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end
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endtask
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@@ -242,6 +245,37 @@ module tb_usb_data_interface;
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end
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endtask
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// Set data_pending flags directly via hierarchical access.
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// This is the standard TB technique for internal state setup —
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// bypasses the CDC path for immediate, reliable flag setting.
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// Call BEFORE assert_range_valid in tests that need SEND_DOPPLER/DETECT.
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task preload_pending_data;
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begin
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@(posedge ft601_clk_in);
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uut.doppler_data_pending = 1'b1;
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uut.cfar_data_pending = 1'b1;
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@(posedge ft601_clk_in);
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end
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endtask
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// Set only doppler pending (no cfar)
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task preload_doppler_pending;
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begin
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@(posedge ft601_clk_in);
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uut.doppler_data_pending = 1'b1;
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@(posedge ft601_clk_in);
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end
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endtask
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// Set only cfar pending (no doppler)
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task preload_cfar_pending;
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begin
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@(posedge ft601_clk_in);
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uut.cfar_data_pending = 1'b1;
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@(posedge ft601_clk_in);
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end
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endtask
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// ── Helper: wait for read FSM to reach a specific state ───
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task wait_for_read_state;
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input [2:0] target;
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@@ -296,6 +330,8 @@ module tb_usb_data_interface;
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input [15:0] di;
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input det;
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begin
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// Pre-load pending flags so FSM enters doppler/cfar states
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preload_pending_data;
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assert_range_valid(rng);
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wait_for_state(S_SEND_DOPPLER, 100);
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pulse_doppler_once(dr, di);
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@@ -356,6 +392,7 @@ module tb_usb_data_interface;
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// Stall at SEND_HEADER so we can verify first range word later
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ft601_txe = 1;
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preload_pending_data;
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assert_range_valid(32'hDEAD_BEEF);
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wait_for_state(S_SEND_HEADER, 50);
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repeat (2) @(posedge ft601_clk_in); #1;
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@@ -430,13 +467,17 @@ module tb_usb_data_interface;
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apply_reset;
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ft601_txe = 0;
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// Preload only doppler pending (not cfar) so the FSM sends
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// doppler data. After doppler, SEND_DETECT sees cfar_data_pending=0
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// and skips to SEND_FOOTER, then WAIT_ACK, then IDLE.
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preload_doppler_pending;
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assert_range_valid(32'h0000_0001);
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wait_for_state(S_SEND_DOPPLER, 100);
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#1;
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check(uut.current_state === S_SEND_DOPPLER,
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"Reached SEND_DOPPLER_DATA");
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// Provide doppler data
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// Provide doppler data via valid pulse (updates captured values)
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@(posedge clk);
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doppler_real = 16'hAAAA;
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doppler_imag = 16'h5555;
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@@ -451,33 +492,34 @@ module tb_usb_data_interface;
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check(uut.doppler_imag_cap === 16'h5555,
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"doppler_imag captured correctly");
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// Pump remaining doppler pulses
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pulse_doppler_once(16'hAAAA, 16'h5555);
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pulse_doppler_once(16'hAAAA, 16'h5555);
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pulse_doppler_once(16'hAAAA, 16'h5555);
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wait_for_state(S_SEND_DETECT, 100);
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// The FSM has doppler_data_pending set and sends 4 bytes, then
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// transitions past SEND_DETECT (cfar_data_pending=0) to IDLE.
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wait_for_state(S_IDLE, 100);
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#1;
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check(uut.current_state === S_SEND_DETECT,
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"Doppler complete, moved to SEND_DETECTION_DATA");
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check(uut.current_state === S_IDLE,
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"Doppler done, packet completed");
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// ════════════════════════════════════════════════════════
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// TEST GROUP 5: CFAR detection data
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// ════════════════════════════════════════════════════════
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$display("\n--- Test Group 5: CFAR Detection Data ---");
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// Continue from SEND_DETECTION_DATA state
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check(uut.current_state === S_SEND_DETECT,
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// Start a new packet with both doppler and cfar pending to verify
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// cfar data is properly sent in SEND_DETECTION_DATA.
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apply_reset;
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ft601_txe = 0;
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preload_pending_data;
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assert_range_valid(32'h0000_0002);
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// FSM races through: HEADER -> RANGE -> DOPPLER -> DETECT -> FOOTER -> IDLE
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// All pending flags consumed proves SEND_DETECT was entered.
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wait_for_state(S_IDLE, 200);
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#1;
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check(uut.cfar_data_pending === 1'b0,
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"Starting in SEND_DETECTION_DATA");
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pulse_cfar_once(1'b1);
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// After CFAR pulse, the FSM should advance to SEND_FOOTER
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// The pulse may take a few cycles to propagate
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wait_for_state(S_SEND_FOOTER, 50);
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// Check if we passed through detect -> footer, or further
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check(uut.current_state === S_SEND_FOOTER ||
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uut.current_state === S_WAIT_ACK ||
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uut.current_state === S_IDLE,
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// Verify the full packet completed with cfar data consumed
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check(uut.current_state === S_IDLE &&
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uut.doppler_data_pending === 1'b0 &&
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uut.cfar_data_pending === 1'b0,
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"CFAR detection sent, FSM advanced past SEND_DETECTION_DATA");
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|
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// ════════════════════════════════════════════════════════
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@@ -494,6 +536,7 @@ module tb_usb_data_interface;
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ft601_txe = 0;
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// Drive packet through range data
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preload_pending_data;
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assert_range_valid(32'hFACE_FEED);
|
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wait_for_state(S_SEND_DOPPLER, 100);
|
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// Feed doppler data (need 4 pulses)
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@@ -534,6 +577,7 @@ module tb_usb_data_interface;
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// Verify WAIT_ACK behavior by doing another packet and catching it
|
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apply_reset;
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ft601_txe = 0;
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preload_pending_data;
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assert_range_valid(32'h1234_5678);
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wait_for_state(S_SEND_DOPPLER, 100);
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pulse_doppler_once(16'hABCD, 16'hEF01);
|
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@@ -627,6 +671,7 @@ module tb_usb_data_interface;
|
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|
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// Drive a full packet and check WAIT_ACK
|
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ft601_txe = 0;
|
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preload_pending_data;
|
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assert_range_valid(32'h1111_2222);
|
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wait_for_state(S_SEND_DOPPLER, 100);
|
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pulse_doppler_once(16'h3333, 16'h4444);
|
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@@ -726,6 +771,7 @@ module tb_usb_data_interface;
|
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ft601_txe = 0;
|
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|
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// Start a write packet
|
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preload_pending_data;
|
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assert_range_valid(32'hFACE_FEED);
|
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wait_for_state(S_SEND_HEADER, 50);
|
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@(posedge ft601_clk_in); #1;
|
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@@ -774,19 +820,21 @@ module tb_usb_data_interface;
|
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// Wait for CDC propagation (2-stage sync)
|
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repeat (6) @(posedge ft601_clk_in);
|
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|
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// Drive range valid — this should trigger the write FSM
|
||||
// Preload cfar pending so the FSM enters the SEND_DETECT data path
|
||||
// (without it, SEND_DETECT skips immediately on !cfar_data_pending).
|
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preload_cfar_pending;
|
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// Drive range valid — triggers write FSM
|
||||
assert_range_valid(32'hAA11_BB22);
|
||||
// FSM: IDLE -> SEND_HEADER -> SEND_RANGE_DATA (doppler disabled) -> SEND_DETECTION_DATA -> SEND_FOOTER
|
||||
// With ft601_txe=0, SEND_RANGE completes in 4 cycles so we may not catch it.
|
||||
// Wait for SEND_DETECT (which proves range was sent and doppler was skipped).
|
||||
wait_for_state(S_SEND_DETECT, 200);
|
||||
// FSM: IDLE -> SEND_HEADER -> SEND_RANGE (doppler disabled) -> SEND_DETECT -> FOOTER
|
||||
// The FSM races through SEND_DETECT in 1 cycle (cfar_data_pending is consumed).
|
||||
// Verify the packet completed correctly (doppler was skipped).
|
||||
wait_for_state(S_IDLE, 200);
|
||||
#1;
|
||||
check(uut.current_state === S_SEND_DETECT,
|
||||
// Reaching IDLE proves: HEADER -> RANGE -> (skip DOPPLER) -> DETECT -> FOOTER -> ACK -> IDLE.
|
||||
// cfar_data_pending consumed confirms SEND_DETECT was entered.
|
||||
check(uut.current_state === S_IDLE && uut.cfar_data_pending === 1'b0,
|
||||
"Stream gate: reached SEND_DETECT (range sent, doppler skipped)");
|
||||
|
||||
pulse_cfar_once(1'b1);
|
||||
wait_for_state(S_IDLE, 100);
|
||||
#1;
|
||||
check(uut.current_state === S_IDLE,
|
||||
"Stream gate: packet completed without doppler");
|
||||
|
||||
|
||||
@@ -178,10 +178,21 @@ reg [15:0] doppler_real_cap;
|
||||
reg [15:0] doppler_imag_cap;
|
||||
reg cfar_detection_cap;
|
||||
|
||||
// Data-pending flags (ft601_clk domain).
|
||||
// Set when a valid edge is detected, cleared when the write FSM consumes
|
||||
// or skips the data. Prevents the write FSM from blocking forever when
|
||||
// a stream's valid hasn't fired yet (e.g., Doppler needs 32 chirps).
|
||||
reg doppler_data_pending;
|
||||
reg cfar_data_pending;
|
||||
|
||||
// Gap 2: CDC for stream_control (clk_100m -> ft601_clk_in)
|
||||
// stream_control changes infrequently (only on host USB command), so
|
||||
// per-bit 2-stage synchronizers are sufficient. No Gray coding needed
|
||||
// because the bits are independent enables.
|
||||
// Fix #5: Default to range-only (3'b001) on reset to prevent write FSM
|
||||
// deadlock before host configures streams. With all streams enabled on
|
||||
// reset, the first range_valid triggers the write FSM which then blocks
|
||||
// forever on SEND_DOPPLER_DATA (Doppler hasn't produced data yet).
|
||||
(* ASYNC_REG = "TRUE" *) reg [2:0] stream_ctrl_sync_0;
|
||||
(* ASYNC_REG = "TRUE" *) reg [2:0] stream_ctrl_sync_1;
|
||||
wire stream_range_en = stream_ctrl_sync_1[0];
|
||||
@@ -217,9 +228,11 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
|
||||
doppler_real_cap <= 16'd0;
|
||||
doppler_imag_cap <= 16'd0;
|
||||
cfar_detection_cap <= 1'b0;
|
||||
// Gap 2: stream control CDC reset (default all enabled)
|
||||
stream_ctrl_sync_0 <= 3'b111;
|
||||
stream_ctrl_sync_1 <= 3'b111;
|
||||
doppler_data_pending <= 1'b0;
|
||||
cfar_data_pending <= 1'b0;
|
||||
// Fix #5: Default to range-only on reset (prevents write FSM deadlock)
|
||||
stream_ctrl_sync_0 <= 3'b001;
|
||||
stream_ctrl_sync_1 <= 3'b001;
|
||||
// Gap 2: status request CDC reset
|
||||
status_req_sync <= 2'b00;
|
||||
status_req_sync_prev <= 1'b0;
|
||||
@@ -267,9 +280,12 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
|
||||
if (doppler_valid_sync[1] && !doppler_valid_sync_d) begin
|
||||
doppler_real_cap <= doppler_real_hold;
|
||||
doppler_imag_cap <= doppler_imag_hold;
|
||||
doppler_data_pending <= 1'b1;
|
||||
end
|
||||
if (cfar_valid_sync[1] && !cfar_valid_sync_d)
|
||||
if (cfar_valid_sync[1] && !cfar_valid_sync_d) begin
|
||||
cfar_detection_cap <= cfar_detection_hold;
|
||||
cfar_data_pending <= 1'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
@@ -382,10 +398,12 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
|
||||
current_state <= SEND_STATUS;
|
||||
status_word_idx <= 3'd0;
|
||||
end
|
||||
// Gap 2: Only trigger write FSM if at least one enabled stream has data
|
||||
else if ((range_valid_ft && stream_range_en) ||
|
||||
(doppler_valid_ft && stream_doppler_en) ||
|
||||
(cfar_valid_ft && stream_cfar_en)) begin
|
||||
// Trigger write FSM on range_valid edge (primary data source).
|
||||
// Doppler/cfar data_pending flags are checked inside
|
||||
// SEND_DOPPLER_DATA and SEND_DETECTION_DATA to skip or send.
|
||||
// Do NOT trigger on pending flags alone — they're sticky and
|
||||
// would cause repeated packet starts without new range data.
|
||||
else if (range_valid_ft && stream_range_en) begin
|
||||
// Don't start write if a read is about to begin
|
||||
if (ft601_rxf) begin // rxf=1 means no host data pending
|
||||
current_state <= SEND_HEADER;
|
||||
@@ -442,7 +460,7 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
|
||||
end
|
||||
|
||||
SEND_DOPPLER_DATA: begin
|
||||
if (!ft601_txe && doppler_valid_ft) begin
|
||||
if (!ft601_txe && doppler_data_pending) begin
|
||||
ft601_data_oe <= 1;
|
||||
ft601_be <= 4'b1111;
|
||||
|
||||
@@ -457,7 +475,7 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
|
||||
|
||||
if (byte_counter == 3) begin
|
||||
byte_counter <= 0;
|
||||
// Gap 2: skip disabled cfar stream
|
||||
doppler_data_pending <= 1'b0;
|
||||
if (stream_cfar_en)
|
||||
current_state <= SEND_DETECTION_DATA;
|
||||
else
|
||||
@@ -465,15 +483,26 @@ always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
|
||||
end else begin
|
||||
byte_counter <= byte_counter + 1;
|
||||
end
|
||||
end else if (!doppler_data_pending) begin
|
||||
// No doppler data available yet — skip to next stream
|
||||
byte_counter <= 0;
|
||||
if (stream_cfar_en)
|
||||
current_state <= SEND_DETECTION_DATA;
|
||||
else
|
||||
current_state <= SEND_FOOTER;
|
||||
end
|
||||
end
|
||||
|
||||
SEND_DETECTION_DATA: begin
|
||||
if (!ft601_txe && cfar_valid_ft) begin
|
||||
if (!ft601_txe && cfar_data_pending) begin
|
||||
ft601_data_oe <= 1;
|
||||
ft601_be <= 4'b0001;
|
||||
ft601_data_out <= {24'b0, 7'b0, cfar_detection_cap};
|
||||
ft601_wr_n <= 0;
|
||||
cfar_data_pending <= 1'b0;
|
||||
current_state <= SEND_FOOTER;
|
||||
end else if (!cfar_data_pending) begin
|
||||
// No CFAR data available yet — skip to footer
|
||||
current_state <= SEND_FOOTER;
|
||||
end
|
||||
end
|
||||
|
||||
Reference in New Issue
Block a user