E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)

RTL fixes discovered via new end-to-end testbench:
- plfm_chirp_controller: TX/RX mixer enables now mutually exclusive
  by FSM state (Fix #4), preventing simultaneous TX+RX activation
- usb_data_interface: stream control reset default 3'b001 (range-only),
  added doppler/cfar data_pending sticky flags, write FSM triggers on
  range_valid only — eliminates startup deadlock (Fix #5)
- radar_receiver_final: STM32 toggle signals wired through for mode-00
  pass-through, dynamic frame detection via host_chirps_per_elev
- radar_system_top: STM32 toggle signal wiring to receiver instance
- chirp_memory_loader_param: explicit readmemh range for short chirp

Test infrastructure:
- New tb_system_e2e.v: 46 checks across 12 groups (reset, TX, safety,
  RX, USB R/W, CDC, beam scanning, reset recovery, stream control,
  latency budgets, watchdog)
- tb_usb_data_interface: Tests 21/22/56 updated for data_pending
  architecture (preload flags, verify consumption instead of state)
- tb_chirp_controller: mixer tests T7.1/T7.2 updated for Fix #4
- run_regression.sh: PASS/FAIL regex fixed to match only [PASS]/[FAIL]
  markers, added E2E test entry
- Updated rx_final_doppler_out.csv golden data

9_Firmware/9_2_FPGA/radar_system_top.v

@@ -301,7 +301,7 @@ cdc_adc_to_processing #(
     .src_clk(clk_120m_dac_buf),
     .dst_clk(clk_100m_buf),
     .src_reset_n(sys_reset_120m_n),
-    .dst_reset_n(sys_reset_n),
+    .dst_reset_n(sys_reset_n),
     .src_data(tx_current_chirp),
     .src_valid(1'b1),           // Always valid — counter updates continuously
     .dst_data(tx_current_chirp_sync),
@@ -445,7 +445,13 @@ radar_receiver_final rx_inst (
     .host_guard_cycles(host_guard_cycles),
     .host_short_chirp_cycles(host_short_chirp_cycles),
     .host_short_listen_cycles(host_short_listen_cycles),
-    .host_chirps_per_elev(host_chirps_per_elev)
+    .host_chirps_per_elev(host_chirps_per_elev),
+    // STM32 toggle signals for RX mode controller (mode 00 pass-through).
+    // These are the raw GPIO inputs — the RX mode controller's edge detectors
+    // (inside radar_mode_controller) handle debouncing/edge detection.
+    .stm32_new_chirp_rx(stm32_new_chirp),
+    .stm32_new_elevation_rx(stm32_new_elevation),
+    .stm32_new_azimuth_rx(stm32_new_azimuth)
 );
 
 // ============================================================================