fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

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FPGA timing (400MHz domain WNS: +0.339ns, was +0.002ns):
- DONT_TOUCH on BUFG to prevent AggressiveExplore cascade replication
- NCO→mixer pipeline registers break critical 1.5ns route
- Clock uncertainty reduced 200ps→100ps (adequate guardband)
- Updated golden/cosim references for +1 cycle pipeline latency

STM32 bug fixes:
- Guard uint32_t underflow in processStartFlag (length<4)
- Replace unbounded strcat in getSystemStatusForGUI with snprintf
- Early-return error masking in checkSystemHealth
- Add HAL_Delay in emergency blink loop

GUI bug fixes:
- Remove 0x03 from _HARDWARE_ONLY_OPCODES (was in both sets)
- Wire real error count in V7 diagnostics panel
- Fix _stop_demo showing 'Live' label during replay mode

FPGA comment fixes + CI: add test_v7.py to pytest command

Vivado build 50t passed: 0 failing endpoints, WHS=+0.056ns

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This commit is contained in:

Jason

2026-04-14 00:08:26 +05:45

parent b4d1869582

commit 063fa081fe

12 changed files with 4323 additions and 4262 deletions

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9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv

+2048 -2048

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9_Firmware/9_2_FPGA/tb/golden/golden_doppler.mem

+2150 -2150

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