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fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

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FPGA timing (400MHz domain WNS: +0.339ns, was +0.002ns):
- DONT_TOUCH on BUFG to prevent AggressiveExplore cascade replication
- NCO→mixer pipeline registers break critical 1.5ns route
- Clock uncertainty reduced 200ps→100ps (adequate guardband)
- Updated golden/cosim references for +1 cycle pipeline latency

STM32 bug fixes:
- Guard uint32_t underflow in processStartFlag (length<4)
- Replace unbounded strcat in getSystemStatusForGUI with snprintf
- Early-return error masking in checkSystemHealth
- Add HAL_Delay in emergency blink loop

GUI bug fixes:
- Remove 0x03 from _HARDWARE_ONLY_OPCODES (was in both sets)
- Wire real error count in V7 diagnostics panel
- Fix _stop_demo showing 'Live' label during replay mode

FPGA comment fixes + CI: add test_v7.py to pytest command

Vivado build 50t passed: 0 failing endpoints, WHS=+0.056ns
This commit is contained in:
Jason
2026-04-14 00:08:26 +05:45
parent b4d1869582
commit 063fa081fe
12 changed files with 4323 additions and 4262 deletions
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9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
+6 -5
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@@ -85,10 +85,11 @@ set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]
set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p]
# --------------------------------------------------------------------------
# Timing margin for 400 MHz CIC critical path
# Timing margin for 400 MHz critical paths
# --------------------------------------------------------------------------
# The CIC decimator at 400 MHz has near-zero margin (WNS = +0.001 ns in
# Build 26). Adding 200 ps of extra setup uncertainty forces Vivado to
# leave comfortable margin for temperature/voltage/aging variation.
# Extra setup uncertainty forces Vivado to leave margin for temperature/voltage/
# aging variation. Reduced from 200 ps to 100 ps after NCO→mixer pipeline
# register fix eliminated the dominant timing bottleneck (WNS went from +0.002ns
# to comfortable margin). 100 ps still provides ~4% guardband on the 2.5ns period.
# This is additive to the existing jitter-based uncertainty (~53 ps).
set_clock_uncertainty -setup -add 0.200 [get_clocks clk_mmcm_out0]
set_clock_uncertainty -setup -add 0.100 [get_clocks clk_mmcm_out0]