feat: add cross-layer contract tests (Python/Verilog/C) with CI job

Three-tier test orchestrator validates opcode maps, bit widths, packet
layouts, and round-trip correctness across FPGA RTL, Python GUI, and
STM32 firmware. Catches 3 real bugs:

- status_words[0] 37-bit truncation in both USB interfaces
- Python radar_mode readback at wrong bit position (bit 21 vs 24)
- RadarSettings.cpp buffer overread (min check 74 vs required 82)

29 tests: 24 pass, 5 xfail (documenting confirmed bugs).
4th CI job added: cross-layer-tests (Python + iverilog + cc).

9_Firmware/tests/cross_layer/.gitignore

@@ -0,0 +1,12 @@
+# Simulation outputs (generated by iverilog TB)
+cmd_results.txt
+data_packet.txt
+status_packet.txt
+*.vcd
+*.vvp
+
+# Compiled C stub
+stm32_stub
+
+# Python
+__pycache__/