fix: align all range/carrier/velocity values to PLFM hardware + FPGA bug fixes
- Correct carrier from 10.525/10 GHz to 10.5 GHz (verified ADF4382 config) - Correct range-per-bin from 4.8/5.6/781.25 m to 24.0 m (matched-filter) - Correct velocity resolution from 1.484 to 2.67 m/s/bin (PRI-based) - Correct processing rate from 4 MSPS to 100 MSPS (post-DDC) - Correct max range from 307/5000/50000 m to 1536 m (64 bins x 24 m) - Add WaveformConfig.pri_s field (167 us PRI for velocity calculation) - Fix short chirp chirp_complete deadlock (Bug A) - Remove dead short_chirp ports, rename long_chirp to ref_chirp (Bug B) - Fix stale latency comment 2159 -> 3187 cycles (Bug C) - Create radar_params.vh as single source of truth for FPGA parameters - Lower RadarSettings.cpp map_size validation bound from 1000 to 100 - Add PLFM hardware constants to golden_reference.py - Update all GUI versions, tests, and cross-layer contracts All 244 tests passing (167 Python + 21 MCU + 29 cross-layer + 27 FPGA)
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@@ -724,8 +724,8 @@ class TestTier3CStub:
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"freq_max": 30.0e6,
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"prf1": 1000.0,
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"prf2": 2000.0,
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"max_distance": 50000.0,
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"map_size": 50000.0,
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"max_distance": 1536.0,
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"map_size": 1536.0,
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}
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pkt = self._build_settings_packet(values)
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result = self._run_stub(stub_binary, pkt)
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@@ -784,11 +784,11 @@ class TestTier3CStub:
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def test_bad_markers_rejected(self, stub_binary):
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"""Packet with wrong start/end markers must be rejected."""
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values = {
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"system_frequency": 10.0e9, "chirp_duration_1": 30.0e-6,
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"system_frequency": 10.5e9, "chirp_duration_1": 30.0e-6,
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"chirp_duration_2": 0.5e-6, "chirps_per_position": 32,
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"freq_min": 10.0e6, "freq_max": 30.0e6,
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"prf1": 1000.0, "prf2": 2000.0,
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"max_distance": 50000.0, "map_size": 50000.0,
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"max_distance": 1536.0, "map_size": 1536.0,
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}
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pkt = self._build_settings_packet(values)
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