fix: align all range/carrier/velocity values to PLFM hardware + FPGA bug fixes
- Correct carrier from 10.525/10 GHz to 10.5 GHz (verified ADF4382 config) - Correct range-per-bin from 4.8/5.6/781.25 m to 24.0 m (matched-filter) - Correct velocity resolution from 1.484 to 2.67 m/s/bin (PRI-based) - Correct processing rate from 4 MSPS to 100 MSPS (post-DDC) - Correct max range from 307/5000/50000 m to 1536 m (64 bins x 24 m) - Add WaveformConfig.pri_s field (167 us PRI for velocity calculation) - Fix short chirp chirp_complete deadlock (Bug A) - Remove dead short_chirp ports, rename long_chirp to ref_chirp (Bug B) - Fix stale latency comment 2159 -> 3187 cycles (Bug C) - Create radar_params.vh as single source of truth for FPGA parameters - Lower RadarSettings.cpp map_size validation bound from 1000 to 100 - Add PLFM hardware constants to golden_reference.py - Update all GUI versions, tests, and cross-layer contracts All 244 tests passing (167 Python + 21 MCU + 29 cross-layer + 27 FPGA)
This commit is contained in:
Jason
@@ -18,10 +18,9 @@ module matched_filter_multi_segment (
|
||||
input wire mc_new_elevation, // Toggle for new elevation (32)
|
||||
input wire mc_new_azimuth, // Toggle for new azimuth (50)
|
||||
|
||||
input wire [15:0] long_chirp_real,
|
||||
input wire [15:0] long_chirp_imag,
|
||||
input wire [15:0] short_chirp_real,
|
||||
input wire [15:0] short_chirp_imag,
|
||||
// Reference chirp (upstream memory loader selects long/short via use_long_chirp)
|
||||
input wire [15:0] ref_chirp_real,
|
||||
input wire [15:0] ref_chirp_imag,
|
||||
|
||||
// Memory system interface
|
||||
output reg [1:0] segment_request,
|
||||
@@ -244,6 +243,7 @@ always @(posedge clk or negedge reset_n) begin
|
||||
if (!use_long_chirp) begin
|
||||
if (chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1) begin
|
||||
state <= ST_ZERO_PAD;
|
||||
chirp_complete <= 1; // Bug A fix: mark chirp done so ST_OUTPUT exits to IDLE
|
||||
`ifdef SIMULATION
|
||||
$display("[MULTI_SEG_FIXED] Short chirp: collected %d samples, starting zero-pad",
|
||||
chirp_samples_collected + 1);
|
||||
@@ -500,11 +500,9 @@ matched_filter_processing_chain m_f_p_c(
|
||||
// Chirp Selection
|
||||
.chirp_counter(chirp_counter),
|
||||
|
||||
// Reference Chirp Memory Interfaces
|
||||
.long_chirp_real(long_chirp_real),
|
||||
.long_chirp_imag(long_chirp_imag),
|
||||
.short_chirp_real(short_chirp_real),
|
||||
.short_chirp_imag(short_chirp_imag),
|
||||
// Reference Chirp Memory Interface (single pair — upstream selects long/short)
|
||||
.ref_chirp_real(ref_chirp_real),
|
||||
.ref_chirp_imag(ref_chirp_imag),
|
||||
|
||||
// Output
|
||||
.range_profile_i(fft_pc_i),
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
* .clk, .reset_n
|
||||
* .adc_data_i, .adc_data_q, .adc_valid <- from input buffer
|
||||
* .chirp_counter <- 6-bit frame counter
|
||||
* .long_chirp_real/imag, .short_chirp_real/imag <- reference (time-domain)
|
||||
* .ref_chirp_real/imag <- reference (time-domain)
|
||||
* .range_profile_i, .range_profile_q, .range_profile_valid -> output
|
||||
* .chain_state -> 4-bit status
|
||||
*
|
||||
@@ -48,10 +48,10 @@ module matched_filter_processing_chain (
|
||||
input wire [5:0] chirp_counter,
|
||||
|
||||
// Reference chirp (time-domain, latency-aligned by upstream buffer)
|
||||
input wire [15:0] long_chirp_real,
|
||||
input wire [15:0] long_chirp_imag,
|
||||
input wire [15:0] short_chirp_real,
|
||||
input wire [15:0] short_chirp_imag,
|
||||
// Upstream chirp_memory_loader_param selects long/short reference
|
||||
// via use_long_chirp — this single pair carries whichever is active.
|
||||
input wire [15:0] ref_chirp_real,
|
||||
input wire [15:0] ref_chirp_imag,
|
||||
|
||||
// Output: range profile (pulse-compressed)
|
||||
output wire signed [15:0] range_profile_i,
|
||||
@@ -189,8 +189,8 @@ always @(posedge clk or negedge reset_n) begin
|
||||
// Store first sample (signal + reference)
|
||||
fwd_buf_i[0] <= $signed(adc_data_i);
|
||||
fwd_buf_q[0] <= $signed(adc_data_q);
|
||||
ref_buf_i[0] <= $signed(long_chirp_real);
|
||||
ref_buf_q[0] <= $signed(long_chirp_imag);
|
||||
ref_buf_i[0] <= $signed(ref_chirp_real);
|
||||
ref_buf_q[0] <= $signed(ref_chirp_imag);
|
||||
fwd_in_count <= 1;
|
||||
state <= ST_FWD_FFT;
|
||||
end
|
||||
@@ -205,8 +205,8 @@ always @(posedge clk or negedge reset_n) begin
|
||||
if (adc_valid && fwd_in_count < FFT_SIZE) begin
|
||||
fwd_buf_i[fwd_in_count] <= $signed(adc_data_i);
|
||||
fwd_buf_q[fwd_in_count] <= $signed(adc_data_q);
|
||||
ref_buf_i[fwd_in_count] <= $signed(long_chirp_real);
|
||||
ref_buf_q[fwd_in_count] <= $signed(long_chirp_imag);
|
||||
ref_buf_i[fwd_in_count] <= $signed(ref_chirp_real);
|
||||
ref_buf_q[fwd_in_count] <= $signed(ref_chirp_imag);
|
||||
fwd_in_count <= fwd_in_count + 1;
|
||||
end
|
||||
|
||||
@@ -775,16 +775,16 @@ always @(posedge clk) begin : ref_bram_port
|
||||
if (adc_valid) begin
|
||||
we = 1'b1;
|
||||
addr = 0;
|
||||
wdata_i = $signed(long_chirp_real);
|
||||
wdata_q = $signed(long_chirp_imag);
|
||||
wdata_i = $signed(ref_chirp_real);
|
||||
wdata_q = $signed(ref_chirp_imag);
|
||||
end
|
||||
end
|
||||
ST_COLLECT: begin
|
||||
if (adc_valid && collect_count < FFT_SIZE) begin
|
||||
we = 1'b1;
|
||||
addr = collect_count[ADDR_BITS-1:0];
|
||||
wdata_i = $signed(long_chirp_real);
|
||||
wdata_q = $signed(long_chirp_imag);
|
||||
wdata_i = $signed(ref_chirp_real);
|
||||
wdata_q = $signed(ref_chirp_imag);
|
||||
end
|
||||
end
|
||||
ST_REF_FFT: begin
|
||||
|
||||
@@ -0,0 +1,200 @@
|
||||
// ============================================================================
|
||||
// radar_params.vh — Single Source of Truth for AERIS-10 FPGA Parameters
|
||||
// ============================================================================
|
||||
//
|
||||
// ALL modules in the FPGA processing chain MUST `include this file instead of
|
||||
// hardcoding range bins, segment counts, chirp samples, or timing values.
|
||||
//
|
||||
// This file uses `define macros (not localparam) so it can be included at any
|
||||
// scope. Each consuming module should include this file inside its body and
|
||||
// optionally alias macros to localparams for readability.
|
||||
//
|
||||
// BOARD VARIANTS:
|
||||
// SUPPORT_LONG_RANGE = 0 (50T, USB_MODE=1) — 3 km mode only, 64 range bins
|
||||
// SUPPORT_LONG_RANGE = 1 (200T, USB_MODE=0) — 3 km + 20 km modes, up to 1024 bins
|
||||
//
|
||||
// RANGE MODES (runtime, via host_range_mode register, opcode 0x20):
|
||||
// 2'b00 = 3 km (default on both boards)
|
||||
// 2'b01 = 20 km (200T only; clamped to 3 km on 50T)
|
||||
// 2'b10 = Reserved
|
||||
// 2'b11 = Reserved
|
||||
//
|
||||
// USAGE:
|
||||
// `include "radar_params.vh"
|
||||
// Then reference `RP_FFT_SIZE, `RP_MAX_OUTPUT_BINS, etc.
|
||||
//
|
||||
// PHYSICAL CONSTANTS (derived from hardware):
|
||||
// ADC clock: 400 MSPS
|
||||
// CIC decimation: 4x
|
||||
// Processing rate: 100 MSPS (post-DDC)
|
||||
// Range per sample: c / (2 * 100e6) = 1.5 m
|
||||
// Decimation factor: 16 (1024 FFT bins -> 64 output bins per segment)
|
||||
// Range per dec. bin: 1.5 m * 16 = 24.0 m
|
||||
// Carrier frequency: 10.5 GHz
|
||||
//
|
||||
// CHIRP BANDWIDTH (Phase 1 target — currently 20 MHz, planned 30 MHz):
|
||||
// Range resolution: c / (2 * BW)
|
||||
// 20 MHz -> 7.5 m
|
||||
// 30 MHz -> 5.0 m
|
||||
// NOTE: Range resolution is independent of range-per-bin. Resolution
|
||||
// determines the minimum separation between two targets; range-per-bin
|
||||
// determines the spatial sampling grid.
|
||||
// ============================================================================
|
||||
|
||||
`ifndef RADAR_PARAMS_VH
|
||||
`define RADAR_PARAMS_VH
|
||||
|
||||
// ============================================================================
|
||||
// BOARD VARIANT — set at synthesis time, NOT runtime
|
||||
// ============================================================================
|
||||
// Default to 50T (conservative). Override in top-level or synthesis script:
|
||||
// +define+SUPPORT_LONG_RANGE
|
||||
// or via Vivado: set_property verilog_define {SUPPORT_LONG_RANGE} [current_fileset]
|
||||
|
||||
// Note: SUPPORT_LONG_RANGE is a flag define (ifdef/ifndef), not a value.
|
||||
// `ifndef SUPPORT_LONG_RANGE means 50T (no long range).
|
||||
// `ifdef SUPPORT_LONG_RANGE means 200T (long range supported).
|
||||
|
||||
// ============================================================================
|
||||
// FFT AND PROCESSING CONSTANTS (fixed, both modes)
|
||||
// ============================================================================
|
||||
|
||||
`define RP_FFT_SIZE 1024 // Range FFT points per segment
|
||||
`define RP_OVERLAP_SAMPLES 128 // Overlap between adjacent segments
|
||||
`define RP_SEGMENT_ADVANCE 896 // FFT_SIZE - OVERLAP = 1024 - 128
|
||||
`define RP_DECIMATION_FACTOR 16 // Range bin decimation (1024 -> 64)
|
||||
`define RP_BINS_PER_SEGMENT 64 // FFT_SIZE / DECIMATION_FACTOR
|
||||
`define RP_DOPPLER_FFT_SIZE 16 // Per sub-frame Doppler FFT
|
||||
`define RP_CHIRPS_PER_FRAME 32 // Total chirps (16 long + 16 short)
|
||||
`define RP_CHIRPS_PER_SUBFRAME 16 // Chirps per Doppler sub-frame
|
||||
`define RP_NUM_DOPPLER_BINS 32 // 2 sub-frames * 16 = 32
|
||||
`define RP_DATA_WIDTH 16 // ADC/processing data width
|
||||
|
||||
// ============================================================================
|
||||
// 3 KM MODE PARAMETERS (both 50T and 200T)
|
||||
// ============================================================================
|
||||
|
||||
`define RP_LONG_CHIRP_SAMPLES_3KM 3000 // 30 us at 100 MSPS
|
||||
`define RP_LONG_SEGMENTS_3KM 4 // ceil((3000-1024)/896) + 1 = 4
|
||||
`define RP_OUTPUT_RANGE_BINS_3KM 64 // Downstream pipeline expects 64 range bins (NOTE: will become 128 after 2048-pt FFT upgrade)
|
||||
`define RP_SHORT_CHIRP_SAMPLES 50 // 0.5 us at 100 MSPS (same both modes)
|
||||
`define RP_SHORT_SEGMENTS 1 // Single segment for short chirp
|
||||
|
||||
// Derived 3 km limits
|
||||
`define RP_MAX_RANGE_3KM 1536 // 64 bins * 24 m = 1536 m
|
||||
|
||||
// ============================================================================
|
||||
// 20 KM MODE PARAMETERS (200T only)
|
||||
// ============================================================================
|
||||
|
||||
`define RP_LONG_CHIRP_SAMPLES_20KM 13700 // 137 us at 100 MSPS (= listen window)
|
||||
`define RP_LONG_SEGMENTS_20KM 16 // ceil((13700-1024)/896) + 1 = 16
|
||||
`define RP_OUTPUT_RANGE_BINS_20KM 1024 // 16 segments * 64 dec. bins each
|
||||
|
||||
// Derived 20 km limits
|
||||
`define RP_MAX_RANGE_20KM 24576 // 1024 bins * 24 m = 24576 m
|
||||
|
||||
// ============================================================================
|
||||
// MAX VALUES (for sizing buffers — compile-time, based on board variant)
|
||||
// ============================================================================
|
||||
|
||||
`ifdef SUPPORT_LONG_RANGE
|
||||
`define RP_MAX_SEGMENTS 16
|
||||
`define RP_MAX_OUTPUT_BINS 1024
|
||||
`define RP_MAX_CHIRP_SAMPLES 13700
|
||||
`else
|
||||
`define RP_MAX_SEGMENTS 4
|
||||
`define RP_MAX_OUTPUT_BINS 64
|
||||
`define RP_MAX_CHIRP_SAMPLES 3000
|
||||
`endif
|
||||
|
||||
// ============================================================================
|
||||
// BIT WIDTHS (derived from MAX values)
|
||||
// ============================================================================
|
||||
|
||||
// Segment index: ceil(log2(MAX_SEGMENTS))
|
||||
// 50T: log2(4) = 2 bits
|
||||
// 200T: log2(16) = 4 bits
|
||||
`ifdef SUPPORT_LONG_RANGE
|
||||
`define RP_SEGMENT_IDX_WIDTH 4
|
||||
`define RP_RANGE_BIN_WIDTH 10
|
||||
`define RP_CHIRP_MEM_ADDR_W 14 // log2(16*1024) = 14
|
||||
`define RP_DOPPLER_MEM_ADDR_W 15 // log2(1024*32) = 15
|
||||
`define RP_CFAR_MAG_ADDR_W 15 // log2(1024*32) = 15
|
||||
`else
|
||||
`define RP_SEGMENT_IDX_WIDTH 2
|
||||
`define RP_RANGE_BIN_WIDTH 6
|
||||
`define RP_CHIRP_MEM_ADDR_W 12 // log2(4*1024) = 12
|
||||
`define RP_DOPPLER_MEM_ADDR_W 11 // log2(64*32) = 11
|
||||
`define RP_CFAR_MAG_ADDR_W 11 // log2(64*32) = 11
|
||||
`endif
|
||||
|
||||
// Derived depths (for memory declarations)
|
||||
// Usage: reg [15:0] mem [0:`RP_CHIRP_MEM_DEPTH-1];
|
||||
`define RP_CHIRP_MEM_DEPTH (`RP_MAX_SEGMENTS * `RP_FFT_SIZE)
|
||||
`define RP_DOPPLER_MEM_DEPTH (`RP_MAX_OUTPUT_BINS * `RP_CHIRPS_PER_FRAME)
|
||||
`define RP_CFAR_MAG_DEPTH (`RP_MAX_OUTPUT_BINS * `RP_NUM_DOPPLER_BINS)
|
||||
|
||||
// ============================================================================
|
||||
// CHIRP TIMING DEFAULTS (100 MHz clock cycles)
|
||||
// ============================================================================
|
||||
// Reset defaults for host-configurable timing registers.
|
||||
// Match radar_mode_controller.v parameters and main.cpp STM32 defaults.
|
||||
|
||||
`define RP_DEF_LONG_CHIRP_CYCLES 3000 // 30 us
|
||||
`define RP_DEF_LONG_LISTEN_CYCLES 13700 // 137 us
|
||||
`define RP_DEF_GUARD_CYCLES 17540 // 175.4 us
|
||||
`define RP_DEF_SHORT_CHIRP_CYCLES 50 // 0.5 us
|
||||
`define RP_DEF_SHORT_LISTEN_CYCLES 17450 // 174.5 us
|
||||
`define RP_DEF_CHIRPS_PER_ELEV 32
|
||||
|
||||
// ============================================================================
|
||||
// BLIND ZONE CONSTANTS (informational, for comments and GUI)
|
||||
// ============================================================================
|
||||
// Long chirp blind zone: c * 30 us / 2 = 4500 m
|
||||
// Short chirp blind zone: c * 0.5 us / 2 = 75 m
|
||||
|
||||
`define RP_LONG_BLIND_ZONE_M 4500
|
||||
`define RP_SHORT_BLIND_ZONE_M 75
|
||||
|
||||
// ============================================================================
|
||||
// PHYSICAL CONSTANTS (integer-scaled for Verilog — use in comments/assertions)
|
||||
// ============================================================================
|
||||
// Range per ADC sample: 1.5 m (stored as 15 in units of 0.1 m)
|
||||
// Range per decimated bin: 24.0 m (stored as 240 in units of 0.1 m)
|
||||
// Processing rate: 100 MSPS
|
||||
|
||||
`define RP_RANGE_PER_SAMPLE_DM 15 // 1.5 m in decimeters
|
||||
`define RP_RANGE_PER_BIN_DM 240 // 24.0 m in decimeters
|
||||
`define RP_PROCESSING_RATE_MHZ 100
|
||||
|
||||
// ============================================================================
|
||||
// AGC DEFAULTS
|
||||
// ============================================================================
|
||||
`define RP_DEF_AGC_TARGET 200
|
||||
`define RP_DEF_AGC_ATTACK 1
|
||||
`define RP_DEF_AGC_DECAY 1
|
||||
`define RP_DEF_AGC_HOLDOFF 4
|
||||
|
||||
// ============================================================================
|
||||
// CFAR DEFAULTS
|
||||
// ============================================================================
|
||||
`define RP_DEF_CFAR_GUARD 2
|
||||
`define RP_DEF_CFAR_TRAIN 8
|
||||
`define RP_DEF_CFAR_ALPHA 8'h30 // 3.0 in Q4.4
|
||||
`define RP_DEF_CFAR_MODE 2'b00 // CA-CFAR
|
||||
|
||||
// ============================================================================
|
||||
// DETECTION DEFAULTS
|
||||
// ============================================================================
|
||||
`define RP_DEF_DETECT_THRESHOLD 10000
|
||||
|
||||
// ============================================================================
|
||||
// RANGE MODE ENCODING
|
||||
// ============================================================================
|
||||
`define RP_RANGE_MODE_3KM 2'b00
|
||||
`define RP_RANGE_MODE_20KM 2'b01
|
||||
`define RP_RANGE_MODE_RSVD2 2'b10
|
||||
`define RP_RANGE_MODE_RSVD3 2'b11
|
||||
|
||||
`endif // RADAR_PARAMS_VH
|
||||
@@ -102,9 +102,9 @@ wire [7:0] gc_saturation_count; // Diagnostic: per-frame clipped sample counter
|
||||
wire [7:0] gc_peak_magnitude; // Diagnostic: per-frame peak magnitude
|
||||
wire [3:0] gc_current_gain; // Diagnostic: effective gain_shift
|
||||
|
||||
// Reference signals for the processing chain
|
||||
wire [15:0] long_chirp_real, long_chirp_imag;
|
||||
wire [15:0] short_chirp_real, short_chirp_imag;
|
||||
// Reference signal for the processing chain (carries long OR short ref
|
||||
// depending on use_long_chirp — selected by chirp_memory_loader_param)
|
||||
wire [15:0] ref_chirp_real, ref_chirp_imag;
|
||||
|
||||
// ========== DOPPLER PROCESSING SIGNALS ==========
|
||||
wire [31:0] range_data_32bit;
|
||||
@@ -292,7 +292,8 @@ end
|
||||
// sample_addr_wire removed — was unused implicit wire (synthesis warning)
|
||||
|
||||
// 4. CRITICAL: Reference Chirp Latency Buffer
|
||||
// This aligns reference data with FFT output (2159 cycle delay)
|
||||
// This aligns reference data with FFT output (3187 cycle delay)
|
||||
// TODO: verify empirically during hardware bring-up with correlation test
|
||||
wire [15:0] delayed_ref_i, delayed_ref_q;
|
||||
wire mem_ready_delayed;
|
||||
|
||||
@@ -308,11 +309,10 @@ latency_buffer #(
|
||||
.valid_out(mem_ready_delayed)
|
||||
);
|
||||
|
||||
// Assign delayed reference signals
|
||||
assign long_chirp_real = delayed_ref_i;
|
||||
assign long_chirp_imag = delayed_ref_q;
|
||||
assign short_chirp_real = delayed_ref_i;
|
||||
assign short_chirp_imag = delayed_ref_q;
|
||||
// Assign delayed reference signals (single pair — chirp_memory_loader_param
|
||||
// selects long/short reference upstream via use_long_chirp)
|
||||
assign ref_chirp_real = delayed_ref_i;
|
||||
assign ref_chirp_imag = delayed_ref_q;
|
||||
|
||||
// 5. Dual Chirp Matched Filter
|
||||
|
||||
@@ -336,10 +336,8 @@ matched_filter_multi_segment mf_dual (
|
||||
.mc_new_chirp(mc_new_chirp),
|
||||
.mc_new_elevation(mc_new_elevation),
|
||||
.mc_new_azimuth(mc_new_azimuth),
|
||||
.long_chirp_real(delayed_ref_i), // From latency buffer
|
||||
.long_chirp_imag(delayed_ref_q),
|
||||
.short_chirp_real(delayed_ref_i), // Same for short chirp
|
||||
.short_chirp_imag(delayed_ref_q),
|
||||
.ref_chirp_real(delayed_ref_i), // From latency buffer (long or short ref)
|
||||
.ref_chirp_imag(delayed_ref_q),
|
||||
.segment_request(segment_request),
|
||||
.mem_request(mem_request),
|
||||
.sample_addr_out(sample_addr_from_chain),
|
||||
|
||||
@@ -2,8 +2,8 @@
|
||||
"""
|
||||
golden_reference.py — AERIS-10 FPGA bit-accurate golden reference model
|
||||
|
||||
Uses ADI CN0566 Phaser radar data (10.525 GHz X-band FMCW) to validate
|
||||
the FPGA signal processing pipeline stage by stage:
|
||||
Uses ADI CN0566 Phaser radar data (10.525 GHz, used as test stimulus only) to
|
||||
validate the FPGA signal processing pipeline stage by stage:
|
||||
|
||||
ADC → DDC (NCO+mixer+CIC+FIR) → Range FFT → Doppler FFT → Detection
|
||||
|
||||
@@ -90,7 +90,8 @@ HAMMING_Q15 = [
|
||||
0x3088, 0x1B6D, 0x0E5C, 0x0A3D,
|
||||
]
|
||||
|
||||
# ADI dataset parameters
|
||||
# ADI dataset parameters — used ONLY for loading/requantizing ADI Phaser test data.
|
||||
# These are NOT PLFM hardware parameters. See AERIS-10 constants below.
|
||||
ADI_SAMPLE_RATE = 4e6 # 4 MSPS
|
||||
ADI_IF_FREQ = 100e3 # 100 kHz IF
|
||||
ADI_RF_FREQ = 9.9e9 # 9.9 GHz
|
||||
@@ -99,9 +100,17 @@ ADI_RAMP_TIME = 300e-6 # 300 us
|
||||
ADI_NUM_CHIRPS = 256
|
||||
ADI_SAMPLES_PER_CHIRP = 1079
|
||||
|
||||
# AERIS-10 parameters
|
||||
AERIS_FS = 400e6 # 400 MHz ADC clock
|
||||
AERIS_IF = 120e6 # 120 MHz IF
|
||||
# AERIS-10 hardware parameters (from ADF4382/AD9523/main.cpp configuration)
|
||||
AERIS_FS = 400e6 # 400 MHz ADC clock (AD9523 OUT4)
|
||||
AERIS_IF = 120e6 # 120 MHz IF (TX 10.5 GHz - RX 10.38 GHz)
|
||||
AERIS_FS_PROCESSING = 100e6 # Post-DDC rate (400 MSPS / 4x CIC)
|
||||
AERIS_CARRIER_HZ = 10.5e9 # TX LO (ADF4382, verified)
|
||||
AERIS_RX_LO_HZ = 10.38e9 # RX LO (ADF4382)
|
||||
AERIS_CHIRP_BW = 20e6 # Chirp bandwidth (target: 30 MHz Phase 1)
|
||||
AERIS_LONG_CHIRP_S = 30e-6 # Long chirp duration
|
||||
AERIS_PRI_S = 167e-6 # Pulse repetition interval
|
||||
AERIS_DECIMATION = 16 # Range bin decimation (1024 → 64)
|
||||
AERIS_RANGE_PER_BIN = 24.0 # Meters per decimated bin
|
||||
|
||||
|
||||
# ===========================================================================
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -421,13 +421,13 @@ def test_latency_buffer():
|
||||
#
|
||||
# For synthesis: the latency_buffer feeds ref data to the chain via
|
||||
# chirp_memory_loader_param → latency_buffer → chain.
|
||||
# But wait — looking at radar_receiver_final.v:
|
||||
# Looking at radar_receiver_final.v:
|
||||
# - mem_request drives valid_in on the latency buffer
|
||||
# - The buffer delays {ref_i, ref_q} by LATENCY valid_in cycles
|
||||
# - The delayed output feeds long_chirp_real/imag → chain
|
||||
# - The delayed output feeds ref_chirp_real/imag → chain
|
||||
#
|
||||
# The purpose: the chain in the SYNTHESIS branch reads reference data
|
||||
# via the long_chirp_real/imag ports DURING ST_FWD_FFT (while collecting
|
||||
# via the ref_chirp_real/imag ports DURING ST_FWD_FFT (while collecting
|
||||
# input samples). The reference data needs to arrive LATENCY cycles
|
||||
# after the first mem_request, where LATENCY accounts for:
|
||||
# - The fft_engine pipeline latency from input to output
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -18,10 +18,8 @@ module tb_matched_filter_processing_chain;
|
||||
reg [15:0] adc_data_q;
|
||||
reg adc_valid;
|
||||
reg [5:0] chirp_counter;
|
||||
reg [15:0] long_chirp_real;
|
||||
reg [15:0] long_chirp_imag;
|
||||
reg [15:0] short_chirp_real;
|
||||
reg [15:0] short_chirp_imag;
|
||||
reg [15:0] ref_chirp_real;
|
||||
reg [15:0] ref_chirp_imag;
|
||||
wire signed [15:0] range_profile_i;
|
||||
wire signed [15:0] range_profile_q;
|
||||
wire range_profile_valid;
|
||||
@@ -83,10 +81,8 @@ module tb_matched_filter_processing_chain;
|
||||
.adc_data_q (adc_data_q),
|
||||
.adc_valid (adc_valid),
|
||||
.chirp_counter (chirp_counter),
|
||||
.long_chirp_real (long_chirp_real),
|
||||
.long_chirp_imag (long_chirp_imag),
|
||||
.short_chirp_real (short_chirp_real),
|
||||
.short_chirp_imag (short_chirp_imag),
|
||||
.ref_chirp_real (ref_chirp_real),
|
||||
.ref_chirp_imag (ref_chirp_imag),
|
||||
.range_profile_i (range_profile_i),
|
||||
.range_profile_q (range_profile_q),
|
||||
.range_profile_valid (range_profile_valid),
|
||||
@@ -133,10 +129,8 @@ module tb_matched_filter_processing_chain;
|
||||
adc_data_i = 16'd0;
|
||||
adc_data_q = 16'd0;
|
||||
chirp_counter = 6'd0;
|
||||
long_chirp_real = 16'd0;
|
||||
long_chirp_imag = 16'd0;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'd0;
|
||||
ref_chirp_imag = 16'd0;
|
||||
cap_enable = 0;
|
||||
cap_count = 0;
|
||||
cap_max_abs = 0;
|
||||
@@ -168,10 +162,8 @@ module tb_matched_filter_processing_chain;
|
||||
angle = 6.28318530718 * tone_bin * k / (1.0 * FFT_SIZE);
|
||||
adc_data_i = $rtoi(8000.0 * $cos(angle));
|
||||
adc_data_q = $rtoi(8000.0 * $sin(angle));
|
||||
long_chirp_real = $rtoi(8000.0 * $cos(angle));
|
||||
long_chirp_imag = $rtoi(8000.0 * $sin(angle));
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = $rtoi(8000.0 * $cos(angle));
|
||||
ref_chirp_imag = $rtoi(8000.0 * $sin(angle));
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk);
|
||||
#1;
|
||||
@@ -187,10 +179,8 @@ module tb_matched_filter_processing_chain;
|
||||
for (k = 0; k < FFT_SIZE; k = k + 1) begin
|
||||
adc_data_i = 16'sh1000;
|
||||
adc_data_q = 16'sh0000;
|
||||
long_chirp_real = 16'sh1000;
|
||||
long_chirp_imag = 16'sh0000;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'sh1000;
|
||||
ref_chirp_imag = 16'sh0000;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk);
|
||||
#1;
|
||||
@@ -233,10 +223,8 @@ module tb_matched_filter_processing_chain;
|
||||
for (k = 0; k < FFT_SIZE; k = k + 1) begin
|
||||
adc_data_i = gold_sig_i[k];
|
||||
adc_data_q = gold_sig_q[k];
|
||||
long_chirp_real = gold_ref_i[k];
|
||||
long_chirp_imag = gold_ref_q[k];
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = gold_ref_i[k];
|
||||
ref_chirp_imag = gold_ref_q[k];
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk);
|
||||
#1;
|
||||
@@ -374,10 +362,8 @@ module tb_matched_filter_processing_chain;
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
adc_data_i = 16'd0;
|
||||
adc_data_q = 16'd0;
|
||||
long_chirp_real = 16'd0;
|
||||
long_chirp_imag = 16'd0;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'd0;
|
||||
ref_chirp_imag = 16'd0;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
@@ -449,10 +435,8 @@ module tb_matched_filter_processing_chain;
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
adc_data_i = $rtoi(8000.0 * $cos(6.28318530718 * 5 * i / 1024.0));
|
||||
adc_data_q = $rtoi(8000.0 * $sin(6.28318530718 * 5 * i / 1024.0));
|
||||
long_chirp_real = $rtoi(8000.0 * $cos(6.28318530718 * 10 * i / 1024.0));
|
||||
long_chirp_imag = $rtoi(8000.0 * $sin(6.28318530718 * 10 * i / 1024.0));
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = $rtoi(8000.0 * $cos(6.28318530718 * 10 * i / 1024.0));
|
||||
ref_chirp_imag = $rtoi(8000.0 * $sin(6.28318530718 * 10 * i / 1024.0));
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
@@ -568,10 +552,8 @@ module tb_matched_filter_processing_chain;
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
adc_data_i = 16'sh7FFF;
|
||||
adc_data_q = 16'sh7FFF;
|
||||
long_chirp_real = 16'sh7FFF;
|
||||
long_chirp_imag = 16'sh7FFF;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'sh7FFF;
|
||||
ref_chirp_imag = 16'sh7FFF;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
@@ -589,10 +571,8 @@ module tb_matched_filter_processing_chain;
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
adc_data_i = 16'sh8000;
|
||||
adc_data_q = 16'sh8000;
|
||||
long_chirp_real = 16'sh8000;
|
||||
long_chirp_imag = 16'sh8000;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'sh8000;
|
||||
ref_chirp_imag = 16'sh8000;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
@@ -611,16 +591,14 @@ module tb_matched_filter_processing_chain;
|
||||
if (i % 2 == 0) begin
|
||||
adc_data_i = 16'sh7FFF;
|
||||
adc_data_q = 16'sh7FFF;
|
||||
long_chirp_real = 16'sh7FFF;
|
||||
long_chirp_imag = 16'sh7FFF;
|
||||
ref_chirp_real = 16'sh7FFF;
|
||||
ref_chirp_imag = 16'sh7FFF;
|
||||
end else begin
|
||||
adc_data_i = 16'sh8000;
|
||||
adc_data_q = 16'sh8000;
|
||||
long_chirp_real = 16'sh8000;
|
||||
long_chirp_imag = 16'sh8000;
|
||||
ref_chirp_real = 16'sh8000;
|
||||
ref_chirp_imag = 16'sh8000;
|
||||
end
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
@@ -641,10 +619,8 @@ module tb_matched_filter_processing_chain;
|
||||
for (i = 0; i < 512; i = i + 1) begin
|
||||
adc_data_i = 16'sh1000;
|
||||
adc_data_q = 16'sh0000;
|
||||
long_chirp_real = 16'sh1000;
|
||||
long_chirp_imag = 16'sh0000;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'sh1000;
|
||||
ref_chirp_imag = 16'sh0000;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
@@ -683,10 +659,8 @@ module tb_matched_filter_processing_chain;
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
adc_data_i = 16'sh1000;
|
||||
adc_data_q = 16'sh0000;
|
||||
long_chirp_real = 16'sh1000;
|
||||
long_chirp_imag = 16'sh0000;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'sh1000;
|
||||
ref_chirp_imag = 16'sh0000;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
|
||||
|
||||
@@ -28,10 +28,8 @@ module tb_mf_chain_synth;
|
||||
reg [15:0] adc_data_q;
|
||||
reg adc_valid;
|
||||
reg [5:0] chirp_counter;
|
||||
reg [15:0] long_chirp_real;
|
||||
reg [15:0] long_chirp_imag;
|
||||
reg [15:0] short_chirp_real;
|
||||
reg [15:0] short_chirp_imag;
|
||||
reg [15:0] ref_chirp_real;
|
||||
reg [15:0] ref_chirp_imag;
|
||||
wire signed [15:0] range_profile_i;
|
||||
wire signed [15:0] range_profile_q;
|
||||
wire range_profile_valid;
|
||||
@@ -78,10 +76,8 @@ module tb_mf_chain_synth;
|
||||
.adc_data_q (adc_data_q),
|
||||
.adc_valid (adc_valid),
|
||||
.chirp_counter (chirp_counter),
|
||||
.long_chirp_real (long_chirp_real),
|
||||
.long_chirp_imag (long_chirp_imag),
|
||||
.short_chirp_real (short_chirp_real),
|
||||
.short_chirp_imag (short_chirp_imag),
|
||||
.ref_chirp_real (ref_chirp_real),
|
||||
.ref_chirp_imag (ref_chirp_imag),
|
||||
.range_profile_i (range_profile_i),
|
||||
.range_profile_q (range_profile_q),
|
||||
.range_profile_valid (range_profile_valid),
|
||||
@@ -130,10 +126,8 @@ module tb_mf_chain_synth;
|
||||
adc_data_i = 16'd0;
|
||||
adc_data_q = 16'd0;
|
||||
chirp_counter = 6'd0;
|
||||
long_chirp_real = 16'd0;
|
||||
long_chirp_imag = 16'd0;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'd0;
|
||||
ref_chirp_imag = 16'd0;
|
||||
cap_enable = 0;
|
||||
cap_count = 0;
|
||||
cap_max_abs = 0;
|
||||
@@ -177,10 +171,8 @@ module tb_mf_chain_synth;
|
||||
for (k = 0; k < FFT_SIZE; k = k + 1) begin
|
||||
adc_data_i = 16'sh1000; // +4096
|
||||
adc_data_q = 16'sh0000;
|
||||
long_chirp_real = 16'sh1000;
|
||||
long_chirp_imag = 16'sh0000;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'sh1000;
|
||||
ref_chirp_imag = 16'sh0000;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk);
|
||||
#1;
|
||||
@@ -199,10 +191,8 @@ module tb_mf_chain_synth;
|
||||
angle = 6.28318530718 * tone_bin * k / (1.0 * FFT_SIZE);
|
||||
adc_data_i = $rtoi(8000.0 * $cos(angle));
|
||||
adc_data_q = $rtoi(8000.0 * $sin(angle));
|
||||
long_chirp_real = $rtoi(8000.0 * $cos(angle));
|
||||
long_chirp_imag = $rtoi(8000.0 * $sin(angle));
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = $rtoi(8000.0 * $cos(angle));
|
||||
ref_chirp_imag = $rtoi(8000.0 * $sin(angle));
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk);
|
||||
#1;
|
||||
@@ -219,16 +209,14 @@ module tb_mf_chain_synth;
|
||||
if (k == 0) begin
|
||||
adc_data_i = 16'sh4000; // 0.5 in Q15
|
||||
adc_data_q = 16'sh0000;
|
||||
long_chirp_real = 16'sh4000;
|
||||
long_chirp_imag = 16'sh0000;
|
||||
ref_chirp_real = 16'sh4000;
|
||||
ref_chirp_imag = 16'sh0000;
|
||||
end else begin
|
||||
adc_data_i = 16'sh0000;
|
||||
adc_data_q = 16'sh0000;
|
||||
long_chirp_real = 16'sh0000;
|
||||
long_chirp_imag = 16'sh0000;
|
||||
ref_chirp_real = 16'sh0000;
|
||||
ref_chirp_imag = 16'sh0000;
|
||||
end
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk);
|
||||
#1;
|
||||
@@ -309,10 +297,8 @@ module tb_mf_chain_synth;
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
adc_data_i = 16'd0;
|
||||
adc_data_q = 16'd0;
|
||||
long_chirp_real = 16'd0;
|
||||
long_chirp_imag = 16'd0;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'd0;
|
||||
ref_chirp_imag = 16'd0;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
@@ -379,10 +365,8 @@ module tb_mf_chain_synth;
|
||||
for (i = 0; i < 512; i = i + 1) begin
|
||||
adc_data_i = 16'sh1000;
|
||||
adc_data_q = 16'sh0000;
|
||||
long_chirp_real = 16'sh1000;
|
||||
long_chirp_imag = 16'sh0000;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'sh1000;
|
||||
ref_chirp_imag = 16'sh0000;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
@@ -439,10 +423,8 @@ module tb_mf_chain_synth;
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
adc_data_i = $rtoi(8000.0 * $cos(6.28318530718 * 5 * i / 1024.0));
|
||||
adc_data_q = $rtoi(8000.0 * $sin(6.28318530718 * 5 * i / 1024.0));
|
||||
long_chirp_real = $rtoi(8000.0 * $cos(6.28318530718 * 10 * i / 1024.0));
|
||||
long_chirp_imag = $rtoi(8000.0 * $sin(6.28318530718 * 10 * i / 1024.0));
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = $rtoi(8000.0 * $cos(6.28318530718 * 10 * i / 1024.0));
|
||||
ref_chirp_imag = $rtoi(8000.0 * $sin(6.28318530718 * 10 * i / 1024.0));
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
@@ -469,10 +451,8 @@ module tb_mf_chain_synth;
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
adc_data_i = 16'sh7FFF;
|
||||
adc_data_q = 16'sh7FFF;
|
||||
long_chirp_real = 16'sh7FFF;
|
||||
long_chirp_imag = 16'sh7FFF;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'sh7FFF;
|
||||
ref_chirp_imag = 16'sh7FFF;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
end
|
||||
@@ -495,10 +475,8 @@ module tb_mf_chain_synth;
|
||||
for (i = 0; i < FFT_SIZE; i = i + 1) begin
|
||||
adc_data_i = 16'sh1000;
|
||||
adc_data_q = 16'sh0000;
|
||||
long_chirp_real = 16'sh1000;
|
||||
long_chirp_imag = 16'sh0000;
|
||||
short_chirp_real = 16'd0;
|
||||
short_chirp_imag = 16'd0;
|
||||
ref_chirp_real = 16'sh1000;
|
||||
ref_chirp_imag = 16'sh0000;
|
||||
adc_valid = 1'b1;
|
||||
@(posedge clk); #1;
|
||||
|
||||
|
||||
@@ -88,10 +88,8 @@ reg [15:0] adc_data_i;
|
||||
reg [15:0] adc_data_q;
|
||||
reg adc_valid;
|
||||
reg [5:0] chirp_counter;
|
||||
reg [15:0] long_chirp_real;
|
||||
reg [15:0] long_chirp_imag;
|
||||
reg [15:0] short_chirp_real;
|
||||
reg [15:0] short_chirp_imag;
|
||||
reg [15:0] ref_chirp_real;
|
||||
reg [15:0] ref_chirp_imag;
|
||||
|
||||
wire signed [15:0] range_profile_i;
|
||||
wire signed [15:0] range_profile_q;
|
||||
@@ -108,10 +106,8 @@ matched_filter_processing_chain dut (
|
||||
.adc_data_q(adc_data_q),
|
||||
.adc_valid(adc_valid),
|
||||
.chirp_counter(chirp_counter),
|
||||
.long_chirp_real(long_chirp_real),
|
||||
.long_chirp_imag(long_chirp_imag),
|
||||
.short_chirp_real(short_chirp_real),
|
||||
.short_chirp_imag(short_chirp_imag),
|
||||
.ref_chirp_real(ref_chirp_real),
|
||||
.ref_chirp_imag(ref_chirp_imag),
|
||||
.range_profile_i(range_profile_i),
|
||||
.range_profile_q(range_profile_q),
|
||||
.range_profile_valid(range_profile_valid),
|
||||
@@ -157,10 +153,8 @@ task apply_reset;
|
||||
adc_data_q <= 16'd0;
|
||||
adc_valid <= 1'b0;
|
||||
chirp_counter <= 6'd0;
|
||||
long_chirp_real <= 16'd0;
|
||||
long_chirp_imag <= 16'd0;
|
||||
short_chirp_real <= 16'd0;
|
||||
short_chirp_imag <= 16'd0;
|
||||
ref_chirp_real <= 16'd0;
|
||||
ref_chirp_imag <= 16'd0;
|
||||
repeat(4) @(posedge clk);
|
||||
reset_n <= 1'b1;
|
||||
@(posedge clk);
|
||||
@@ -201,18 +195,16 @@ initial begin
|
||||
@(posedge clk);
|
||||
adc_data_i <= sig_mem_i[i];
|
||||
adc_data_q <= sig_mem_q[i];
|
||||
long_chirp_real <= ref_mem_i[i];
|
||||
long_chirp_imag <= ref_mem_q[i];
|
||||
short_chirp_real <= 16'd0;
|
||||
short_chirp_imag <= 16'd0;
|
||||
ref_chirp_real <= ref_mem_i[i];
|
||||
ref_chirp_imag <= ref_mem_q[i];
|
||||
adc_valid <= 1'b1;
|
||||
end
|
||||
@(posedge clk);
|
||||
adc_valid <= 1'b0;
|
||||
adc_data_i <= 16'd0;
|
||||
adc_data_q <= 16'd0;
|
||||
long_chirp_real <= 16'd0;
|
||||
long_chirp_imag <= 16'd0;
|
||||
ref_chirp_real <= 16'd0;
|
||||
ref_chirp_imag <= 16'd0;
|
||||
|
||||
$display("All samples fed. Waiting for processing...");
|
||||
|
||||
|
||||
@@ -56,10 +56,8 @@ reg [5:0] chirp_counter;
|
||||
reg mc_new_chirp;
|
||||
reg mc_new_elevation;
|
||||
reg mc_new_azimuth;
|
||||
reg [15:0] long_chirp_real;
|
||||
reg [15:0] long_chirp_imag;
|
||||
reg [15:0] short_chirp_real;
|
||||
reg [15:0] short_chirp_imag;
|
||||
reg [15:0] ref_chirp_real;
|
||||
reg [15:0] ref_chirp_imag;
|
||||
reg mem_ready;
|
||||
|
||||
wire signed [15:0] pc_i_w;
|
||||
@@ -84,10 +82,8 @@ matched_filter_multi_segment dut (
|
||||
.mc_new_chirp(mc_new_chirp),
|
||||
.mc_new_elevation(mc_new_elevation),
|
||||
.mc_new_azimuth(mc_new_azimuth),
|
||||
.long_chirp_real(long_chirp_real),
|
||||
.long_chirp_imag(long_chirp_imag),
|
||||
.short_chirp_real(short_chirp_real),
|
||||
.short_chirp_imag(short_chirp_imag),
|
||||
.ref_chirp_real(ref_chirp_real),
|
||||
.ref_chirp_imag(ref_chirp_imag),
|
||||
.segment_request(segment_request),
|
||||
.sample_addr_out(sample_addr_out),
|
||||
.mem_request(mem_request),
|
||||
@@ -123,11 +119,11 @@ end
|
||||
always @(posedge clk) begin
|
||||
if (mem_request) begin
|
||||
if (use_long_chirp) begin
|
||||
long_chirp_real <= ref_mem_i[{segment_request, sample_addr_out}];
|
||||
long_chirp_imag <= ref_mem_q[{segment_request, sample_addr_out}];
|
||||
ref_chirp_real <= ref_mem_i[{segment_request, sample_addr_out}];
|
||||
ref_chirp_imag <= ref_mem_q[{segment_request, sample_addr_out}];
|
||||
end else begin
|
||||
short_chirp_real <= ref_mem_i[sample_addr_out];
|
||||
short_chirp_imag <= ref_mem_q[sample_addr_out];
|
||||
ref_chirp_real <= ref_mem_i[sample_addr_out];
|
||||
ref_chirp_imag <= ref_mem_q[sample_addr_out];
|
||||
end
|
||||
mem_ready <= 1'b1;
|
||||
end else begin
|
||||
@@ -176,10 +172,8 @@ task apply_reset;
|
||||
mc_new_chirp <= 1'b0;
|
||||
mc_new_elevation <= 1'b0;
|
||||
mc_new_azimuth <= 1'b0;
|
||||
long_chirp_real <= 16'd0;
|
||||
long_chirp_imag <= 16'd0;
|
||||
short_chirp_real <= 16'd0;
|
||||
short_chirp_imag <= 16'd0;
|
||||
ref_chirp_real <= 16'd0;
|
||||
ref_chirp_imag <= 16'd0;
|
||||
mem_ready <= 1'b0;
|
||||
repeat(10) @(posedge clk);
|
||||
reset_n <= 1'b1;
|
||||
|
||||
Reference in New Issue
Block a user