Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)
Complete FPGA timing closure across all clock domains after 9 iterative Vivado builds. WNS improved from -48.325ns to +0.018ns (107,886 endpoints). RTL fixes for 400 MHz timing: - NCO: 6-stage pipeline with DSP48E1 phase accumulator, registered LUT index (Fix D splits address decode from ROM read), distributed RAM - CIC: explicit DSP48E1 PCOUT->PCIN cascade for 5 integrator stages, CREG=1 on integrator_0 to eliminate fabric->DSP setup violation - DDC: 400 MHz reset synchronizer (async-assert/sync-deassert), active-high reset register for DSP48E1 RST ports, posedge output stage - FIR: 5-stage binary adder tree pipeline (7-cycle latency) - FFT: 5-cycle butterfly pipeline with registered twiddle index, XPM_MEMORY_TDPRAM for data storage - XDC: CDC false paths, async reset false paths, CIC comb multicycle paths Final Build 9 timing (all MET): adc_dco_p (400 MHz): WNS = +0.278ns clk_100m (100 MHz): WNS = +0.018ns clk_120m_dac (120 MHz): WNS = +0.992ns ft601_clk_in (100 MHz): WNS = +5.229ns Cross-domain (adc_dco_p->clk_100m): WNS = +7.105ns
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Jason
@@ -16,23 +16,57 @@ parameter COEFF_WIDTH = 18;
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parameter DATA_WIDTH = 18;
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parameter ACCUM_WIDTH = 36;
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// Filter coefficients
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// ============================================================================
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// Pipelined FIR filter for 100 MHz timing closure
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//
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// Problem: The original fully-combinatorial adder tree for 32 multiply products
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// created a 31-deep DSP48E1 PCOUT cascade chain taking 56.6ns (WNS = -48.325ns).
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//
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// Solution: 5-stage pipelined binary adder tree with registered outputs at
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// each level. Each stage performs at most one pairwise addition (~1.7ns DSP hop),
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// easily fitting in the 10ns clock period.
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//
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// Pipeline stages:
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// Cycle 0: data_valid → shift delay line, start multiplies (combinatorial)
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// Cycle 1: Register 32 multiply results + 16 pairwise sums (level 0)
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// Cycle 2: 8 pairwise sums (level 1)
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// Cycle 3: 4 pairwise sums (level 2)
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// Cycle 4: 2 pairwise sums (level 3)
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// Cycle 5: 1 final sum → accumulator_reg (level 4)
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// Cycle 6: Output saturation/rounding (existing output stage)
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//
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// Total latency: 7 cycles from data_valid to data_out_valid
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// Throughput: 1 sample per cycle (fully pipelined)
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// FIR runs at 100 MHz on data decimated 4:1 from 400 MHz — valid samples
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// arrive every ~4 cycles, so the 7-cycle latency is transparent.
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// ============================================================================
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// Filter coefficients (symmetric: coeff[k] == coeff[31-k])
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reg signed [COEFF_WIDTH-1:0] coeff [0:TAPS-1];
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// Parallel delay line
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reg signed [DATA_WIDTH-1:0] delay_line [0:TAPS-1];
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// Parallel multiply-accumulate structure
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// Parallel multiply results (combinatorial)
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wire signed [DATA_WIDTH+COEFF_WIDTH-1:0] mult_result [0:TAPS-1];
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// Wires for parallel addition (combinatorial)
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wire signed [ACCUM_WIDTH-1:0] sum_stage1_0, sum_stage1_1, sum_stage1_2, sum_stage1_3;
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wire signed [ACCUM_WIDTH-1:0] sum_stage2_0, sum_stage2_1;
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wire signed [ACCUM_WIDTH-1:0] sum_stage3;
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// Registered accumulator
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// Pipelined adder tree registers
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// Level 0: 16 pairwise sums of 32 products
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reg signed [ACCUM_WIDTH-1:0] add_l0 [0:15];
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// Level 1: 8 pairwise sums
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reg signed [ACCUM_WIDTH-1:0] add_l1 [0:7];
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// Level 2: 4 pairwise sums
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reg signed [ACCUM_WIDTH-1:0] add_l2 [0:3];
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// Level 3: 2 pairwise sums
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reg signed [ACCUM_WIDTH-1:0] add_l3 [0:1];
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// Level 4: final sum
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reg signed [ACCUM_WIDTH-1:0] accumulator_reg;
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// Valid pipeline: 7-stage shift register
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// [0]=multiply done, [1]=L0 done, [2]=L1 done, [3]=L2 done,
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// [4]=L3 done, [5]=L4/accum done, [6]=output done
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reg [6:0] valid_pipe;
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// Initialize coefficients
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initial begin
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// Proper low-pass filter coefficients
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@@ -46,7 +80,7 @@ initial begin
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coeff[28] = 18'sh02A6; coeff[29] = 18'sh3FD87; coeff[30] = 18'sh00CE; coeff[31] = 18'sh00AD;
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end
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// Generate parallel multipliers
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// Generate parallel multipliers (combinatorial — DSP48E1 will absorb these)
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genvar k;
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generate
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for (k = 0; k < TAPS; k = k + 1) begin : mult_gen
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@@ -54,71 +88,135 @@ generate
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end
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endgenerate
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// COMBINATORIAL PARALLEL ADDITION TREE
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// Stage 1: Group of 8
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assign sum_stage1_0 = mult_result[0] + mult_result[1] + mult_result[2] + mult_result[3] +
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mult_result[4] + mult_result[5] + mult_result[6] + mult_result[7];
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assign sum_stage1_1 = mult_result[8] + mult_result[9] + mult_result[10] + mult_result[11] +
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mult_result[12] + mult_result[13] + mult_result[14] + mult_result[15];
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assign sum_stage1_2 = mult_result[16] + mult_result[17] + mult_result[18] + mult_result[19] +
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mult_result[20] + mult_result[21] + mult_result[22] + mult_result[23];
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assign sum_stage1_3 = mult_result[24] + mult_result[25] + mult_result[26] + mult_result[27] +
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mult_result[28] + mult_result[29] + mult_result[30] + mult_result[31];
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// Stage 2: Combine groups of 2
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assign sum_stage2_0 = sum_stage1_0 + sum_stage1_1;
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assign sum_stage2_1 = sum_stage1_2 + sum_stage1_3;
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// Stage 3: Final sum
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assign sum_stage3 = sum_stage2_0 + sum_stage2_1;
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integer i;
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// SINGLE-CYCLE PIPELINE PROCESSING
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// ============================================================================
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// Pipeline Stage 0: Shift delay line on data_valid
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// ============================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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// Reset delay line
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for (i = 0; i < TAPS; i = i + 1) begin
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delay_line[i] <= 0;
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end
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accumulator_reg <= 0;
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data_out <= 0;
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data_out_valid <= 0;
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end else begin
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// Always shift in new data when valid
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if (data_valid) begin
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// Shift delay line
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for (i = TAPS-1; i > 0; i = i - 1) begin
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delay_line[i] <= delay_line[i-1];
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end
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delay_line[0] <= data_in;
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// Register the combinatorial sum
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accumulator_reg <= sum_stage3;
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// Output with 1-cycle latency
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data_out_valid <= 1'b1;
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end else begin
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data_out_valid <= 1'b0;
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end else if (data_valid) begin
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for (i = TAPS-1; i > 0; i = i - 1) begin
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delay_line[i] <= delay_line[i-1];
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end
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// Output saturation logic (registered)
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if (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) begin
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data_out <= (2**(DATA_WIDTH-1))-1;
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end else if (accumulator_reg < -(2**(ACCUM_WIDTH-2))) begin
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data_out <= -(2**(DATA_WIDTH-1));
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end else begin
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// Round and truncate (keep middle bits)
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data_out <= accumulator_reg[ACCUM_WIDTH-2:DATA_WIDTH-1];
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delay_line[0] <= data_in;
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end
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end
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// ============================================================================
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// Pipeline Stage 1 (Level 0): Register 16 pairwise sums of 32 multiply results
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// Each addition is a single 36-bit add — one DSP48E1 hop (~1.7ns), fits 10ns.
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// ============================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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for (i = 0; i < 16; i = i + 1) begin
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add_l0[i] <= 0;
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end
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end else if (valid_pipe[0]) begin
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for (i = 0; i < 16; i = i + 1) begin
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add_l0[i] <= {{(ACCUM_WIDTH-DATA_WIDTH-COEFF_WIDTH){mult_result[2*i][DATA_WIDTH+COEFF_WIDTH-1]}}, mult_result[2*i]} +
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{{(ACCUM_WIDTH-DATA_WIDTH-COEFF_WIDTH){mult_result[2*i+1][DATA_WIDTH+COEFF_WIDTH-1]}}, mult_result[2*i+1]};
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end
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end
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end
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// Always ready to accept new data
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// ============================================================================
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// Pipeline Stage 2 (Level 1): 8 pairwise sums of 16 Level-0 results
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// ============================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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for (i = 0; i < 8; i = i + 1) begin
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add_l1[i] <= 0;
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end
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end else if (valid_pipe[1]) begin
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for (i = 0; i < 8; i = i + 1) begin
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add_l1[i] <= add_l0[2*i] + add_l0[2*i+1];
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end
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end
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end
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// ============================================================================
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// Pipeline Stage 3 (Level 2): 4 pairwise sums of 8 Level-1 results
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// ============================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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for (i = 0; i < 4; i = i + 1) begin
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add_l2[i] <= 0;
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end
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end else if (valid_pipe[2]) begin
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for (i = 0; i < 4; i = i + 1) begin
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add_l2[i] <= add_l1[2*i] + add_l1[2*i+1];
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end
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end
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end
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// ============================================================================
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// Pipeline Stage 4 (Level 3): 2 pairwise sums of 4 Level-2 results
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// ============================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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add_l3[0] <= 0;
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add_l3[1] <= 0;
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end else if (valid_pipe[3]) begin
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add_l3[0] <= add_l2[0] + add_l2[1];
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add_l3[1] <= add_l2[2] + add_l2[3];
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end
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end
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// ============================================================================
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// Pipeline Stage 5 (Level 4): Final sum of 2 Level-3 results
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// ============================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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accumulator_reg <= 0;
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end else if (valid_pipe[4]) begin
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accumulator_reg <= add_l3[0] + add_l3[1];
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end
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end
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// ============================================================================
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// Pipeline Stage 6: Output saturation/rounding (registered)
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// ============================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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data_out <= 0;
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data_out_valid <= 0;
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end else begin
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data_out_valid <= valid_pipe[5];
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if (valid_pipe[5]) begin
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// Output saturation logic
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if (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) begin
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data_out <= (2**(DATA_WIDTH-1))-1;
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end else if (accumulator_reg < -(2**(ACCUM_WIDTH-2))) begin
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data_out <= -(2**(DATA_WIDTH-1));
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end else begin
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// Round and truncate (keep middle bits)
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data_out <= accumulator_reg[ACCUM_WIDTH-2:DATA_WIDTH-1];
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end
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end
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end
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end
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// ============================================================================
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// Valid pipeline shift register
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// ============================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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valid_pipe <= 7'b0000000;
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end else begin
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valid_pipe <= {valid_pipe[5:0], data_valid};
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end
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end
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// Always ready to accept new data (fully pipelined)
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assign fir_ready = 1'b1;
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// Overflow detection (simplified)
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// Overflow detection
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assign filter_overflow = (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) ||
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(accumulator_reg < -(2**(ACCUM_WIDTH-2)));
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endmodule
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endmodule
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