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Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

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Complete FPGA timing closure across all clock domains after 9 iterative
Vivado builds. WNS improved from -48.325ns to +0.018ns (107,886 endpoints).

RTL fixes for 400 MHz timing:
- NCO: 6-stage pipeline with DSP48E1 phase accumulator, registered LUT
  index (Fix D splits address decode from ROM read), distributed RAM
- CIC: explicit DSP48E1 PCOUT->PCIN cascade for 5 integrator stages,
  CREG=1 on integrator_0 to eliminate fabric->DSP setup violation
- DDC: 400 MHz reset synchronizer (async-assert/sync-deassert),
  active-high reset register for DSP48E1 RST ports, posedge output stage
- FIR: 5-stage binary adder tree pipeline (7-cycle latency)
- FFT: 5-cycle butterfly pipeline with registered twiddle index,
  XPM_MEMORY_TDPRAM for data storage
- XDC: CDC false paths, async reset false paths, CIC comb multicycle paths

Final Build 9 timing (all MET):
  adc_dco_p (400 MHz): WNS = +0.278ns
  clk_100m  (100 MHz): WNS = +0.018ns
  clk_120m_dac (120 MHz): WNS = +0.992ns
  ft601_clk_in (100 MHz): WNS = +5.229ns
  Cross-domain (adc_dco_p->clk_100m): WNS = +7.105ns
This commit is contained in:
Jason
2026-03-16 15:02:35 +02:00
parent 692b6a3bfa
commit 00fbab6c9d
7 changed files with 1150 additions and 410 deletions
Download Patch File Download Diff File Expand all files Collapse all files
9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
+648 -219
View File
@@ -15,54 +15,510 @@ parameter STAGES = 5;
parameter DECIMATION = 4;
parameter COMB_DELAY = 1;
// Accumulator width: input_width + N*log2(R) = 18 + 5*2 = 28 bits
// (36-bit was over-provisioned; 28 bits is mathematically exact for R=4, N=5)
localparam ACC_WIDTH = 28;
reg signed [ACC_WIDTH-1:0] integrator [0:STAGES-1];
reg signed [ACC_WIDTH-1:0] comb [0:STAGES-1];
reg signed [ACC_WIDTH-1:0] comb_delay [0:STAGES-1][0:COMB_DELAY-1];
// Enhanced control and monitoring
reg [1:0] decimation_counter;
reg data_valid_delayed;
reg data_valid_comb;
reg [7:0] output_counter;
reg [ACC_WIDTH-1:0] max_integrator_value;
reg overflow_detected;
reg overflow_latched; // Latched overflow indicator
// Diagnostic registers
reg [7:0] saturation_event_count;
reg [31:0] sample_count;
// Comb-stage saturation flags (separate from integrator block to avoid multi-driven nets)
reg comb_overflow_latched;
reg comb_saturation_detected;
reg [7:0] comb_saturation_event_count;
// Temporary signals for calculations
reg signed [ACC_WIDTH-1:0] abs_integrator_value;
reg signed [ACC_WIDTH-1:0] temp_scaled_output;
reg signed [17:0] temp_output; // Temporary output for proper range checking
// Pipeline stage for saturation comparison — breaks CARRY4 chain from timing path
reg sat_pos; // temp_scaled_output > 131071 (registered)
reg sat_neg; // temp_scaled_output < -131072 (registered)
reg signed [17:0] temp_output_pipe; // Registered passthrough value
reg data_out_valid_pipe; // Delayed valid for pipelined output
// Accumulator width: DSP48E1 native 48-bit.
// CIC uses modular (wrapping) arithmetic so extra MSBs are harmless.
localparam ACC_WIDTH = 48;
// Comb section operates on 28-bit (18 + 5*log2(4) = 28, exact for comb range).
localparam COMB_WIDTH = 28;
// ============================================================================
// INTEGRATOR CHAIN — explicit DSP48E1 with PCOUT→PCIN cascade
// ============================================================================
// Integrator[0]: P = P + C, C = sign_extend(data_in) [from fabric]
// Integrator[k]: P = P + PCIN, PCIN from integrator[k-1] [dedicated cascade]
//
// The PCOUT→PCIN cascade uses dedicated silicon routing between vertically
// adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
// on 7-series regardless of speed grade.
//
// Active-high reset derived from reset_n (inverted).
// CEP (clock enable for P register) gated by data_valid.
// ============================================================================
wire reset_h = ~reset_n; // active-high reset for DSP48E1 RSTP
// Sign-extended input for integrator_0 C port (48-bit)
wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
// DSP48E1 cascade wires
wire [47:0] pcout_0, pcout_1, pcout_2, pcout_3;
wire [47:0] p_out_0, p_out_1, p_out_2, p_out_3, p_out_4;
`ifndef SIMULATION
// ============================================================================
// SYNTHESIS: Explicit DSP48E1 instances with PCOUT→PCIN cascade
// ============================================================================
// --- Integrator 0: P = P + C (accumulate sign-extended input) ---
// OPMODE = 7'b0101100: Z=P(010), Y=C(11), X=0(00) → P = P + C
// CREG=1: C port is registered inside DSP48E1. This eliminates the
// fabric→DSP C-port setup timing violation (-0.415ns in Build 6).
// The CREG adds 1 cycle of latency before data reaches the ALU.
// CEC=data_valid gates the C register to match CEP behavior.
DSP48E1 #(
.A_INPUT ("DIRECT"),
.B_INPUT ("DIRECT"),
.USE_DPORT ("FALSE"),
.USE_MULT ("NONE"),
.AUTORESET_PATDET ("NO_RESET"),
.MASK (48'h3FFFFFFFFFFF),
.PATTERN (48'h000000000000),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.ACASCREG (0),
.ADREG (0),
.ALUMODEREG (0),
.AREG (0),
.BCASCREG (0),
.BREG (0),
.CARRYINREG (0),
.CARRYINSELREG (0),
.CREG (1), // C port registered inside DSP — eliminates fabric→DSP setup path
.DREG (0),
.INMODEREG (0),
.MREG (0),
.OPMODEREG (0),
.PREG (1) // P register enabled (accumulator)
) integrator_0_dsp (
.CLK (clk),
.A (30'd0),
.B (18'd0),
.C (data_in_c),
.D (25'd0),
.CARRYIN (1'b0),
.CARRYINSEL (3'b000),
.OPMODE (7'b0101100), // P = P + C
.ALUMODE (4'b0000), // Z + (X + Y + CIN)
.INMODE (5'b00000),
.CEA1 (1'b0),
.CEA2 (1'b0),
.CEB1 (1'b0),
.CEB2 (1'b0),
.CEC (data_valid), // Register C when data is valid (CREG=1)
.CED (1'b0),
.CEM (1'b0),
.CEP (data_valid), // Accumulate only when data is valid
.CEAD (1'b0),
.CEALUMODE (1'b0),
.CECTRL (1'b0),
.CECARRYIN (1'b0),
.CEINMODE (1'b0),
.RSTP (reset_h),
.RSTA (1'b0),
.RSTB (1'b0),
.RSTC (reset_h), // Reset C register (CREG=1) on reset
.RSTD (1'b0),
.RSTM (1'b0),
.RSTALLCARRYIN (1'b0),
.RSTALUMODE (1'b0),
.RSTCTRL (1'b0),
.RSTINMODE (1'b0),
.P (p_out_0),
.PCOUT (pcout_0),
.ACOUT (),
.BCOUT (),
.CARRYCASCOUT (),
.CARRYOUT (),
.MULTSIGNOUT (),
.OVERFLOW (),
.PATTERNBDETECT (),
.PATTERNDETECT (),
.UNDERFLOW ()
);
// --- Integrator 1: P = P + PCIN (cascade from integrator_0) ---
// OPMODE = 7'b0010010: Z=PCIN(001), Y=0(00), X=P(10) → P = P + PCIN
DSP48E1 #(
.A_INPUT ("DIRECT"),
.B_INPUT ("DIRECT"),
.USE_DPORT ("FALSE"),
.USE_MULT ("NONE"),
.AUTORESET_PATDET ("NO_RESET"),
.MASK (48'h3FFFFFFFFFFF),
.PATTERN (48'h000000000000),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.ACASCREG (0),
.ADREG (0),
.ALUMODEREG (0),
.AREG (0),
.BCASCREG (0),
.BREG (0),
.CARRYINREG (0),
.CARRYINSELREG (0),
.CREG (0),
.DREG (0),
.INMODEREG (0),
.MREG (0),
.OPMODEREG (0),
.PREG (1)
) integrator_1_dsp (
.CLK (clk),
.A (30'd0),
.B (18'd0),
.C (48'd0),
.D (25'd0),
.PCIN (pcout_0),
.CARRYIN (1'b0),
.CARRYINSEL (3'b000),
.OPMODE (7'b0010010), // P = P + PCIN
.ALUMODE (4'b0000),
.INMODE (5'b00000),
.CEA1 (1'b0),
.CEA2 (1'b0),
.CEB1 (1'b0),
.CEB2 (1'b0),
.CEC (1'b0),
.CED (1'b0),
.CEM (1'b0),
.CEP (data_valid),
.CEAD (1'b0),
.CEALUMODE (1'b0),
.CECTRL (1'b0),
.CECARRYIN (1'b0),
.CEINMODE (1'b0),
.RSTP (reset_h),
.RSTA (1'b0),
.RSTB (1'b0),
.RSTC (1'b0),
.RSTD (1'b0),
.RSTM (1'b0),
.RSTALLCARRYIN (1'b0),
.RSTALUMODE (1'b0),
.RSTCTRL (1'b0),
.RSTINMODE (1'b0),
.P (p_out_1),
.PCOUT (pcout_1),
.ACOUT (),
.BCOUT (),
.CARRYCASCOUT (),
.CARRYOUT (),
.MULTSIGNOUT (),
.OVERFLOW (),
.PATTERNBDETECT (),
.PATTERNDETECT (),
.UNDERFLOW ()
);
// --- Integrator 2: P = P + PCIN (cascade from integrator_1) ---
DSP48E1 #(
.A_INPUT ("DIRECT"),
.B_INPUT ("DIRECT"),
.USE_DPORT ("FALSE"),
.USE_MULT ("NONE"),
.AUTORESET_PATDET ("NO_RESET"),
.MASK (48'h3FFFFFFFFFFF),
.PATTERN (48'h000000000000),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.ACASCREG (0),
.ADREG (0),
.ALUMODEREG (0),
.AREG (0),
.BCASCREG (0),
.BREG (0),
.CARRYINREG (0),
.CARRYINSELREG (0),
.CREG (0),
.DREG (0),
.INMODEREG (0),
.MREG (0),
.OPMODEREG (0),
.PREG (1)
) integrator_2_dsp (
.CLK (clk),
.A (30'd0),
.B (18'd0),
.C (48'd0),
.D (25'd0),
.PCIN (pcout_1),
.CARRYIN (1'b0),
.CARRYINSEL (3'b000),
.OPMODE (7'b0010010), // P = P + PCIN
.ALUMODE (4'b0000),
.INMODE (5'b00000),
.CEA1 (1'b0),
.CEA2 (1'b0),
.CEB1 (1'b0),
.CEB2 (1'b0),
.CEC (1'b0),
.CED (1'b0),
.CEM (1'b0),
.CEP (data_valid),
.CEAD (1'b0),
.CEALUMODE (1'b0),
.CECTRL (1'b0),
.CECARRYIN (1'b0),
.CEINMODE (1'b0),
.RSTP (reset_h),
.RSTA (1'b0),
.RSTB (1'b0),
.RSTC (1'b0),
.RSTD (1'b0),
.RSTM (1'b0),
.RSTALLCARRYIN (1'b0),
.RSTALUMODE (1'b0),
.RSTCTRL (1'b0),
.RSTINMODE (1'b0),
.P (p_out_2),
.PCOUT (pcout_2),
.ACOUT (),
.BCOUT (),
.CARRYCASCOUT (),
.CARRYOUT (),
.MULTSIGNOUT (),
.OVERFLOW (),
.PATTERNBDETECT (),
.PATTERNDETECT (),
.UNDERFLOW ()
);
// --- Integrator 3: P = P + PCIN (cascade from integrator_2) ---
DSP48E1 #(
.A_INPUT ("DIRECT"),
.B_INPUT ("DIRECT"),
.USE_DPORT ("FALSE"),
.USE_MULT ("NONE"),
.AUTORESET_PATDET ("NO_RESET"),
.MASK (48'h3FFFFFFFFFFF),
.PATTERN (48'h000000000000),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.ACASCREG (0),
.ADREG (0),
.ALUMODEREG (0),
.AREG (0),
.BCASCREG (0),
.BREG (0),
.CARRYINREG (0),
.CARRYINSELREG (0),
.CREG (0),
.DREG (0),
.INMODEREG (0),
.MREG (0),
.OPMODEREG (0),
.PREG (1)
) integrator_3_dsp (
.CLK (clk),
.A (30'd0),
.B (18'd0),
.C (48'd0),
.D (25'd0),
.PCIN (pcout_2),
.CARRYIN (1'b0),
.CARRYINSEL (3'b000),
.OPMODE (7'b0010010), // P = P + PCIN
.ALUMODE (4'b0000),
.INMODE (5'b00000),
.CEA1 (1'b0),
.CEA2 (1'b0),
.CEB1 (1'b0),
.CEB2 (1'b0),
.CEC (1'b0),
.CED (1'b0),
.CEM (1'b0),
.CEP (data_valid),
.CEAD (1'b0),
.CEALUMODE (1'b0),
.CECTRL (1'b0),
.CECARRYIN (1'b0),
.CEINMODE (1'b0),
.RSTP (reset_h),
.RSTA (1'b0),
.RSTB (1'b0),
.RSTC (1'b0),
.RSTD (1'b0),
.RSTM (1'b0),
.RSTALLCARRYIN (1'b0),
.RSTALUMODE (1'b0),
.RSTCTRL (1'b0),
.RSTINMODE (1'b0),
.P (p_out_3),
.PCOUT (pcout_3),
.ACOUT (),
.BCOUT (),
.CARRYCASCOUT (),
.CARRYOUT (),
.MULTSIGNOUT (),
.OVERFLOW (),
.PATTERNBDETECT (),
.PATTERNDETECT (),
.UNDERFLOW ()
);
// --- Integrator 4: P = P + PCIN (cascade from integrator_3) ---
// No PCOUT needed (last stage in cascade)
DSP48E1 #(
.A_INPUT ("DIRECT"),
.B_INPUT ("DIRECT"),
.USE_DPORT ("FALSE"),
.USE_MULT ("NONE"),
.AUTORESET_PATDET ("NO_RESET"),
.MASK (48'h3FFFFFFFFFFF),
.PATTERN (48'h000000000000),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.ACASCREG (0),
.ADREG (0),
.ALUMODEREG (0),
.AREG (0),
.BCASCREG (0),
.BREG (0),
.CARRYINREG (0),
.CARRYINSELREG (0),
.CREG (0),
.DREG (0),
.INMODEREG (0),
.MREG (0),
.OPMODEREG (0),
.PREG (1)
) integrator_4_dsp (
.CLK (clk),
.A (30'd0),
.B (18'd0),
.C (48'd0),
.D (25'd0),
.PCIN (pcout_3),
.CARRYIN (1'b0),
.CARRYINSEL (3'b000),
.OPMODE (7'b0010010), // P = P + PCIN
.ALUMODE (4'b0000),
.INMODE (5'b00000),
.CEA1 (1'b0),
.CEA2 (1'b0),
.CEB1 (1'b0),
.CEB2 (1'b0),
.CEC (1'b0),
.CED (1'b0),
.CEM (1'b0),
.CEP (data_valid),
.CEAD (1'b0),
.CEALUMODE (1'b0),
.CECTRL (1'b0),
.CECARRYIN (1'b0),
.CEINMODE (1'b0),
.RSTP (reset_h),
.RSTA (1'b0),
.RSTB (1'b0),
.RSTC (1'b0),
.RSTD (1'b0),
.RSTM (1'b0),
.RSTALLCARRYIN (1'b0),
.RSTALUMODE (1'b0),
.RSTCTRL (1'b0),
.RSTINMODE (1'b0),
.P (p_out_4),
.PCOUT (),
.ACOUT (),
.BCOUT (),
.CARRYCASCOUT (),
.CARRYOUT (),
.MULTSIGNOUT (),
.OVERFLOW (),
.PATTERNBDETECT (),
.PATTERNDETECT (),
.UNDERFLOW ()
);
`else
// ============================================================================
// SIMULATION: Behavioral model (Icarus Verilog compatible)
// ============================================================================
// Functionally identical: each integrator is P <= P + input, gated by data_valid.
// integrator_0 adds sign-extended data_in; stages 1-4 add previous stage output.
//
// CREG=1 on integrator_0: The C-port register adds 1 cycle of latency.
// data_in_c_delayed models this: on cycle N with data_valid, the DSP's C register
// captures data_in_c(N), but the ALU uses the PREVIOUS C register value.
// So sim_int_0 accumulates data_in_c_delayed (1 cycle behind data_in_c).
// ============================================================================
reg signed [ACC_WIDTH-1:0] sim_int_0, sim_int_1, sim_int_2, sim_int_3, sim_int_4;
reg signed [ACC_WIDTH-1:0] data_in_c_delayed; // Models CREG=1 on integrator_0
always @(posedge clk) begin
if (reset_h) begin
sim_int_0 <= 0;
sim_int_1 <= 0;
sim_int_2 <= 0;
sim_int_3 <= 0;
sim_int_4 <= 0;
data_in_c_delayed <= 0;
end else if (data_valid) begin
// CREG pipeline: capture current data, use previous
data_in_c_delayed <= $signed(data_in_c);
sim_int_0 <= sim_int_0 + data_in_c_delayed;
sim_int_1 <= sim_int_1 + sim_int_0;
sim_int_2 <= sim_int_2 + sim_int_1;
sim_int_3 <= sim_int_3 + sim_int_2;
sim_int_4 <= sim_int_4 + sim_int_3;
end
end
assign p_out_0 = sim_int_0;
assign p_out_1 = sim_int_1;
assign p_out_2 = sim_int_2;
assign p_out_3 = sim_int_3;
assign p_out_4 = sim_int_4;
// pcout wires unused in simulation
assign pcout_0 = sim_int_0;
assign pcout_1 = sim_int_1;
assign pcout_2 = sim_int_2;
assign pcout_3 = sim_int_3;
`endif
// ============================================================================
// CONTROL AND MONITORING (fabric logic)
// ============================================================================
reg signed [COMB_WIDTH-1:0] integrator_sampled;
reg signed [COMB_WIDTH-1:0] comb [0:STAGES-1];
reg signed [COMB_WIDTH-1:0] comb_delay [0:STAGES-1][0:COMB_DELAY-1];
// Enhanced control and monitoring
reg [1:0] decimation_counter;
reg data_valid_delayed;
reg data_valid_comb;
reg [7:0] output_counter;
reg [ACC_WIDTH-1:0] max_integrator_value;
reg overflow_detected;
reg overflow_latched;
// Diagnostic registers
reg [7:0] saturation_event_count;
reg [31:0] sample_count;
// Comb-stage saturation flags
reg comb_overflow_latched;
reg comb_saturation_detected;
reg [7:0] comb_saturation_event_count;
// Temporary signals for calculations
reg signed [ACC_WIDTH-1:0] abs_integrator_value;
reg signed [COMB_WIDTH-1:0] temp_scaled_output;
reg signed [17:0] temp_output;
// Pipeline stage for saturation comparison
reg sat_pos;
reg sat_neg;
reg signed [17:0] temp_output_pipe;
reg data_out_valid_pipe;
integer i, j;
// Initialize
initial begin
for (i = 0; i < STAGES; i = i + 1) begin
integrator[i] = 0;
comb[i] = 0;
for (j = 0; j < COMB_DELAY; j = j + 1) begin
comb_delay[i][j] = 0;
end
end
integrator_sampled = 0;
decimation_counter = 0;
data_valid_delayed = 0;
data_valid_comb = 0;
@@ -77,81 +533,69 @@ initial begin
data_out = 0;
data_out_valid = 0;
abs_integrator_value = 0;
temp_scaled_output = 0;
temp_output = 0;
sat_pos = 0;
sat_neg = 0;
temp_output_pipe = 0;
data_out_valid_pipe = 0;
comb_overflow_latched = 0;
comb_saturation_detected = 0;
comb_saturation_event_count = 0;
temp_scaled_output = 0;
temp_output = 0;
sat_pos = 0;
sat_neg = 0;
temp_output_pipe = 0;
data_out_valid_pipe = 0;
comb_overflow_latched = 0;
comb_saturation_detected = 0;
comb_saturation_event_count = 0;
end
// Enhanced integrator section with proper saturation monitoring
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
for (i = 0; i < STAGES; i = i + 1) begin
integrator[i] <= 0;
end
decimation_counter <= 0;
data_valid_delayed <= 0;
max_integrator_value <= 0;
overflow_detected <= 0;
sample_count <= 0;
abs_integrator_value <= 0;
overflow_latched <= 0;
saturation_detected <= 0;
saturation_event_count <= 0;
max_value_monitor <= 0;
output_counter <= 0;
end else begin
// Monitor control - clear latched saturation on reset_monitors
// (must be inside else branch so Vivado sees a clean async-reset FF template)
if (reset_monitors) begin
overflow_latched <= 0;
saturation_detected <= 0;
max_integrator_value <= 0;
max_value_monitor <= 0;
saturation_event_count <= 0;
end
if (data_valid) begin
sample_count <= sample_count + 1;
// Integrator stages — standard CIC uses wrapping (modular) arithmetic.
// Saturation clamping is removed because CIC math relies on wrap-around;
// the comb stages difference successive integrator values, canceling wraps.
integrator[0] <= integrator[0] + {{(ACC_WIDTH-18){data_in[17]}}, data_in};
// Calculate absolute value for monitoring
abs_integrator_value <= (integrator[0][ACC_WIDTH-1]) ? -integrator[0] : integrator[0];
// Track maximum integrator value for gain monitoring (absolute value)
if (abs_integrator_value > max_integrator_value) begin
max_integrator_value <= abs_integrator_value;
max_value_monitor <= abs_integrator_value[ACC_WIDTH-5:ACC_WIDTH-12];
end
// Remaining integrator stages — pure accumulation, no saturation
for (i = 1; i < STAGES; i = i + 1) begin
integrator[i] <= integrator[i] + integrator[i-1];
end
// Enhanced decimation control
if (decimation_counter == DECIMATION - 1) begin
decimation_counter <= 0;
data_valid_delayed <= 1;
output_counter <= output_counter + 1;
end else begin
decimation_counter <= decimation_counter + 1;
data_valid_delayed <= 0;
end
end else begin
data_valid_delayed <= 0;
overflow_detected <= 1'b0; // Clear immediate detection when no data
end
end
// Decimation control + monitoring (integrators are now DSP48E1 instances)
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
integrator_sampled <= 0;
decimation_counter <= 0;
data_valid_delayed <= 0;
max_integrator_value <= 0;
overflow_detected <= 0;
sample_count <= 0;
abs_integrator_value <= 0;
overflow_latched <= 0;
saturation_detected <= 0;
saturation_event_count <= 0;
max_value_monitor <= 0;
output_counter <= 0;
end else begin
// Monitor control
if (reset_monitors) begin
overflow_latched <= 0;
saturation_detected <= 0;
max_integrator_value <= 0;
max_value_monitor <= 0;
saturation_event_count <= 0;
end
if (data_valid) begin
sample_count <= sample_count + 1;
// Monitor integrator_0 magnitude (read DSP P output)
abs_integrator_value <= (p_out_0[ACC_WIDTH-1]) ? -$signed(p_out_0) : $signed(p_out_0);
if (abs_integrator_value > max_integrator_value) begin
max_integrator_value <= abs_integrator_value;
max_value_monitor <= abs_integrator_value[27:20];
end
// Decimation control
if (decimation_counter == DECIMATION - 1) begin
decimation_counter <= 0;
data_valid_delayed <= 1;
output_counter <= output_counter + 1;
// Capture integrator_4 output, truncate to comb width
integrator_sampled <= p_out_4[COMB_WIDTH-1:0];
end else begin
decimation_counter <= decimation_counter + 1;
data_valid_delayed <= 0;
end
end else begin
data_valid_delayed <= 0;
overflow_detected <= 1'b0;
end
end
end
// Pipeline the valid signal for comb section
@@ -163,116 +607,101 @@ always @(posedge clk or negedge reset_n) begin
end
end
// Enhanced comb section with FIXED scaling and saturation monitoring
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
for (i = 0; i < STAGES; i = i + 1) begin
comb[i] <= 0;
for (j = 0; j < COMB_DELAY; j = j + 1) begin
comb_delay[i][j] <= 0;
end
end
data_out <= 0;
data_out_valid <= 0;
temp_scaled_output <= 0;
temp_output <= 0;
sat_pos <= 0;
sat_neg <= 0;
temp_output_pipe <= 0;
data_out_valid_pipe <= 0;
comb_overflow_latched <= 0;
comb_saturation_detected <= 0;
comb_saturation_event_count <= 0;
end else begin
// Monitor control - clear latched comb saturation on reset_monitors
// (inside else branch so Vivado sees clean async-reset FF template)
if (reset_monitors) begin
comb_overflow_latched <= 0;
comb_saturation_detected <= 0;
comb_saturation_event_count <= 0;
end
if (data_valid_comb) begin
// Comb processing — raw subtraction only (no saturation check needed;
// comb is a differencing stage, cannot overflow if integrators are bounded)
for (i = 0; i < STAGES; i = i + 1) begin
if (i == 0) begin
comb[0] <= integrator[STAGES-1] - comb_delay[0][COMB_DELAY-1];
// Update delay line for first stage
for (j = COMB_DELAY-1; j > 0; j = j - 1) begin
comb_delay[0][j] <= comb_delay[0][j-1];
end
comb_delay[0][0] <= integrator[STAGES-1];
end else begin
comb[i] <= comb[i-1] - comb_delay[i][COMB_DELAY-1];
// Update delay line
for (j = COMB_DELAY-1; j > 0; j = j - 1) begin
comb_delay[i][j] <= comb_delay[i][j-1];
end
comb_delay[i][0] <= comb[i-1];
end
end
// FIXED: Use proper scaling for 5 stages and decimation by 4
// Gain = (4^5) = 1024 = 2^10, so scale by 2^10 to normalize
temp_scaled_output <= comb[STAGES-1] >>> 10;
// FIXED: Extract 18-bit output properly
temp_output <= temp_scaled_output[17:0];
// Pipeline Stage 2: Register saturation comparison flags
// This breaks the CARRY4 chain out of the data_out critical path
sat_pos <= (temp_scaled_output > 131071);
sat_neg <= (temp_scaled_output < -131072);
temp_output_pipe <= temp_scaled_output[17:0];
data_out_valid_pipe <= 1;
end else begin
data_out_valid_pipe <= 0;
end
// Pipeline Stage 3: MUX from registered comparison flags
if (data_out_valid_pipe) begin
if (sat_pos) begin
data_out <= 131071;
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
comb_saturation_event_count <= comb_saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_OUTPUT_SAT: TRUE Positive saturation, final_out=%d", 131071);
`endif
end else if (sat_neg) begin
data_out <= -131072;
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
comb_saturation_event_count <= comb_saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_OUTPUT_SAT: TRUE Negative saturation, final_out=%d", -131072);
`endif
end else begin
data_out <= temp_output_pipe;
comb_overflow_latched <= 1'b0;
comb_saturation_detected <= 1'b0;
end
data_out_valid <= 1;
end else begin
data_out_valid <= 0;
end
end
// Enhanced comb section with scaling and saturation monitoring
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
for (i = 0; i < STAGES; i = i + 1) begin
comb[i] <= 0;
for (j = 0; j < COMB_DELAY; j = j + 1) begin
comb_delay[i][j] <= 0;
end
end
data_out <= 0;
data_out_valid <= 0;
temp_scaled_output <= 0;
temp_output <= 0;
sat_pos <= 0;
sat_neg <= 0;
temp_output_pipe <= 0;
data_out_valid_pipe <= 0;
comb_overflow_latched <= 0;
comb_saturation_detected <= 0;
comb_saturation_event_count <= 0;
end else begin
if (reset_monitors) begin
comb_overflow_latched <= 0;
comb_saturation_detected <= 0;
comb_saturation_event_count <= 0;
end
if (data_valid_comb) begin
for (i = 0; i < STAGES; i = i + 1) begin
if (i == 0) begin
comb[0] <= integrator_sampled - comb_delay[0][COMB_DELAY-1];
for (j = COMB_DELAY-1; j > 0; j = j - 1) begin
comb_delay[0][j] <= comb_delay[0][j-1];
end
comb_delay[0][0] <= integrator_sampled;
end else begin
comb[i] <= comb[i-1] - comb_delay[i][COMB_DELAY-1];
for (j = COMB_DELAY-1; j > 0; j = j - 1) begin
comb_delay[i][j] <= comb_delay[i][j-1];
end
comb_delay[i][0] <= comb[i-1];
end
end
// Gain = (4^5) = 1024 = 2^10, scale by 2^10 to normalize
temp_scaled_output <= comb[STAGES-1] >>> 10;
temp_output <= temp_scaled_output[17:0];
// Pipeline Stage 2: Register saturation comparison flags
sat_pos <= (temp_scaled_output > 131071);
sat_neg <= (temp_scaled_output < -131072);
temp_output_pipe <= temp_scaled_output[17:0];
data_out_valid_pipe <= 1;
end else begin
data_out_valid_pipe <= 0;
end
// Pipeline Stage 3: MUX from registered comparison flags
if (data_out_valid_pipe) begin
if (sat_pos) begin
data_out <= 131071;
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
comb_saturation_event_count <= comb_saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_OUTPUT_SAT: TRUE Positive saturation, final_out=%d", 131071);
`endif
end else if (sat_neg) begin
data_out <= -131072;
comb_overflow_latched <= 1'b1;
comb_saturation_detected <= 1'b1;
comb_saturation_event_count <= comb_saturation_event_count + 1;
`ifdef SIMULATION
$display("CIC_OUTPUT_SAT: TRUE Negative saturation, final_out=%d", -131072);
`endif
end else begin
data_out <= temp_output_pipe;
comb_overflow_latched <= 1'b0;
comb_saturation_detected <= 1'b0;
end
data_out_valid <= 1;
end else begin
data_out_valid <= 0;
end
end
end
// Continuous monitoring of saturation status
`ifdef SIMULATION
always @(posedge clk) begin
if (overflow_detected && sample_count < 100) begin
$display("CIC_OVERFLOW: Immediate detection at sample %0d", sample_count);
end
end
// Continuous monitoring
`ifdef SIMULATION
always @(posedge clk) begin
if (overflow_detected && sample_count < 100) begin
$display("CIC_OVERFLOW: Immediate detection at sample %0d", sample_count);
end
end
`endif
// Clear saturation on external reset — handled in integrator always block
// (lines 165-172, using synchronous check of reset_monitors)
endmodule
endmodule
9_Firmware/9_2_FPGA/cntrt.xdc
+46 -3
View File
@@ -305,9 +305,52 @@ set_property IOSTANDARD LVCMOS33 [get_ports {system_status[*]}]
set_false_path -from [get_ports {stm32_new_*}]
set_false_path -from [get_ports {stm32_mixers_enable}]
# Multicycle paths for slow signals
set_multicycle_path -setup 2 -from [get_clocks clk_100m] -to [get_clocks ft601_clk_in]
set_multicycle_path -hold 1 -from [get_clocks clk_100m] -to [get_clocks ft601_clk_in]
# --------------------------------------------------------------------------
# Async reset recovery/removal false paths
#
# The async reset (reset_n) is held asserted for multiple clock cycles during
# power-on and system reset. The recovery/removal timing checks on CLR pins
# are over-constrained for this use case:
# - reset_sync_reg[1] fans out to 1000+ registers across the FPGA
# - Route delay alone exceeds the clock period (18+ ns for 10ns period)
# - Reset deassertion order is not functionally critical — all registers
# come out of reset within a few cycles of each other
#
# This covers:
# - async_default path group (clk_100m intra-clock, WNS = -11.025ns)
# - clk_100m → clk_120m_dac CDC reset paths (WNS = -3.200ns)
# - clk_100m → ft601_clk_in CDC reset paths (WNS = -3.188ns)
# --------------------------------------------------------------------------
set_false_path -from [get_cells reset_sync_reg[*]] -to [get_pins -filter {REF_PIN_NAME == CLR} -of_objects [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ REGISTER.*.*}]]
# --------------------------------------------------------------------------
# Clock Domain Crossing false paths
#
# These clock domains are asynchronous to each other. Data crossing between
# them uses proper CDC synchronizers (2-stage or 3-stage) with ASYNC_REG
# attributes. The timing tool should not attempt to time these paths as
# single-cycle transfers.
# --------------------------------------------------------------------------
# clk_100m ↔ adc_dco_p (400 MHz): DDC reset synchronizer handles this
# The DDC has an internal 2-stage reset synchronizer for the 400 MHz domain.
# Any remaining CDC paths between these domains use proper synchronizers.
set_false_path -from [get_clocks clk_100m] -to [get_clocks adc_dco_p]
set_false_path -from [get_clocks adc_dco_p] -to [get_clocks clk_100m]
# clk_100m ↔ clk_120m_dac: CDC via synchronizers in radar_system_top
set_false_path -from [get_clocks clk_100m] -to [get_clocks clk_120m_dac]
set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_100m]
# clk_100m ↔ ft601_clk_in: CDC via synchronizers in usb_data_interface
set_false_path -from [get_clocks clk_100m] -to [get_clocks ft601_clk_in]
set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_100m]
# Multicycle paths for slow signals (kept from original constraints)
# NOTE: The false_path above supersedes this for clk_100m→ft601_clk_in,
# but keeping it for documentation of the original design intent.
# set_multicycle_path -setup 2 -from [get_clocks clk_100m] -to [get_clocks ft601_clk_in]
# set_multicycle_path -hold 1 -from [get_clocks clk_100m] -to [get_clocks ft601_clk_in]
# ============================================================================
# PHYSICAL CONSTRAINTS
9_Firmware/9_2_FPGA/ddc_400m.v
+81 -47
View File
@@ -49,15 +49,49 @@ wire [17:0] cic_i_out, cic_q_out;
wire signed [17:0] fir_i_out, fir_q_out;
// Diagnostic registers
reg [2:0] saturation_count;
reg overflow_detected;
reg [7:0] error_counter;
// Diagnostic registers
reg [2:0] saturation_count;
reg overflow_detected;
reg [7:0] error_counter;
// ============================================================================
// 400 MHz Reset Synchronizer
//
// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
// Using it directly as an async reset in the 400 MHz domain causes the reset
// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
// domain, requiring 18.243ns of routing (WNS = -18.081ns).
//
// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
// path from reset_n to all 400 MHz registers). Reset deassertion is
// synchronized to clk_400m rising edge, preventing metastability.
//
// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
// (already synchronized to 100 MHz at radar_system_top level).
// ============================================================================
(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
(* max_fanout = 50 *) reg reset_400m;
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
reset_sync_400m <= 2'b00;
reset_400m <= 1'b1;
end else begin
reset_sync_400m <= {reset_sync_400m[0], 1'b1};
reset_400m <= ~reset_sync_400m[1];
end
end
// CDC synchronization for control signals (2-stage synchronizers)
(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
(* ASYNC_REG = "TRUE" *) reg [1:0] bypass_mode_sync_chain;
(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
wire mixers_enable_sync;
wire bypass_mode_sync;
wire force_saturation_sync;
@@ -108,8 +142,8 @@ assign mixers_enable_sync = mixers_enable_sync_chain[1];
assign bypass_mode_sync = bypass_mode_sync_chain[1];
assign force_saturation_sync = force_saturation_sync_chain[1];
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mixers_enable_sync_chain <= 2'b00;
bypass_mode_sync_chain <= 2'b00;
force_saturation_sync_chain <= 2'b00;
@@ -123,8 +157,8 @@ end
// ============================================================================
// Sample Counter and Debug Monitoring
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n || reset_monitors) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m || reset_monitors) begin
sample_counter <= 0;
error_counter <= 0;
end else if (adc_data_valid_i && adc_data_valid_q ) begin
@@ -136,13 +170,13 @@ end
// ============================================================================
// Enhanced Phase Dithering Instance
// ============================================================================
lfsr_dither_enhanced #(
.DITHER_WIDTH(8)
) phase_dither_gen (
.clk(clk_400m),
.reset_n(reset_n),
.enable(nco_ready),
.dither_out(phase_dither_bits)
lfsr_dither_enhanced #(
.DITHER_WIDTH(8)
) phase_dither_gen (
.clk(clk_400m),
.reset_n(reset_n_400m),
.enable(nco_ready),
.dither_out(phase_dither_bits)
);
// ============================================================================
@@ -152,8 +186,8 @@ lfsr_dither_enhanced #(
localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
// Apply dithering to reduce spurious tones (registered for 400 MHz timing)
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n)
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m)
phase_inc_dithered <= PHASE_INC_120MHZ;
else
phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
@@ -162,9 +196,9 @@ end
// ============================================================================
// Enhanced NCO with Diagnostics
// ============================================================================
nco_400m_enhanced nco_core (
.clk_400m(clk_400m),
.reset_n(reset_n),
nco_400m_enhanced nco_core (
.clk_400m(clk_400m),
.reset_n(reset_n_400m),
.frequency_tuning_word(phase_inc_dithered),
.phase_valid(mixers_enable),
.phase_offset(16'h0000),
@@ -192,8 +226,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
{1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
// Valid pipeline: 3-stage shift register matching DSP48E1 AREG+MREG+PREG latency
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
dsp_valid_pipe <= 3'b000;
end else begin
dsp_valid_pipe <= {dsp_valid_pipe[1:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
@@ -209,8 +243,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal; // Mod
reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg; // Models PREG
// Stage 1: AREG/BREG equivalent
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
adc_signed_reg <= 0;
cos_pipe_reg <= 0;
sin_pipe_reg <= 0;
@@ -222,8 +256,8 @@ always @(posedge clk_400m or negedge reset_n) begin
end
// Stage 2: MREG equivalent
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mult_i_internal <= 0;
mult_q_internal <= 0;
end else begin
@@ -233,8 +267,8 @@ always @(posedge clk_400m or negedge reset_n) begin
end
// Stage 3: PREG equivalent
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mult_i_reg <= 0;
mult_q_reg <= 0;
end else begin
@@ -281,10 +315,10 @@ DSP48E1 #(
) dsp_mixer_i (
// Clock and reset
.CLK(clk_400m),
.RSTA(!reset_n),
.RSTB(!reset_n),
.RSTM(!reset_n),
.RSTP(!reset_n),
.RSTA(reset_400m),
.RSTB(reset_400m),
.RSTM(reset_400m),
.RSTP(reset_400m),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTCTRL(1'b0),
@@ -365,10 +399,10 @@ DSP48E1 #(
.USE_PATTERN_DETECT("NO_PATDET")
) dsp_mixer_q (
.CLK(clk_400m),
.RSTA(!reset_n),
.RSTB(!reset_n),
.RSTM(!reset_n),
.RSTP(!reset_n),
.RSTA(reset_400m),
.RSTB(reset_400m),
.RSTM(reset_400m),
.RSTP(reset_400m),
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTCTRL(1'b0),
@@ -427,8 +461,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
// force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
// polluting the critical input path with extra logic
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mixed_i <= 0;
mixed_q <= 0;
mixed_valid <= 0;
@@ -477,18 +511,18 @@ end
// ============================================================================
wire cic_valid_i, cic_valid_q;
cic_decimator_4x_enhanced cic_i_inst (
.clk(clk_400m),
.reset_n(reset_n),
cic_decimator_4x_enhanced cic_i_inst (
.clk(clk_400m),
.reset_n(reset_n_400m),
.data_in(mixed_i[33:16]),
.data_valid(mixed_valid),
.data_out(cic_i_out),
.data_out_valid(cic_valid_i)
);
cic_decimator_4x_enhanced cic_q_inst (
.clk(clk_400m),
.reset_n(reset_n),
cic_decimator_4x_enhanced cic_q_inst (
.clk(clk_400m),
.reset_n(reset_n_400m),
.data_in(mixed_q[33:16]),
.data_valid(mixed_valid),
.data_out(cic_q_out),
@@ -566,7 +600,7 @@ assign fir_valid = fir_valid_i & fir_valid_q;
// ============================================================================
// Enhanced Output Stage
// ============================================================================
always @(negedge clk_100m or negedge reset_n) begin
always @(posedge clk_100m or negedge reset_n) begin
if (!reset_n) begin
baseband_i_reg <= 0;
baseband_q_reg <= 0;
9_Firmware/9_2_FPGA/fft_engine.v
+117 -31
View File
@@ -8,9 +8,13 @@
*
* Architecture:
* - LOAD: Accept N input samples, store bit-reversed in BRAM
* - COMPUTE: LOG2N stages x N/2 butterflies, 2-cycle pipeline:
* BF_READ: Present BRAM addresses, capture twiddle
* BF_CALC: BRAM data valid; butterfly compute + writeback
* - COMPUTE: LOG2N stages x N/2 butterflies, 5-cycle pipeline:
* BF_READ: Present BRAM addresses; register twiddle index
* BF_TW: BRAM data valid → capture; twiddle ROM lookup from
* registered index → capture cos/sin
* BF_MULT2: DSP multiply from registered data + twiddle
* BF_SHIFT: Arithmetic shift of DSP products
* BF_WRITE: Add/subtract + BRAM writeback
* - OUTPUT: Stream N results (1/N scaling for IFFT)
*
* Data memory uses xpm_memory_tdpram (Xilinx Parameterized Macros) for
@@ -63,14 +67,25 @@ localparam [LOG2N:0] FFT_N_M1 = N - 1;
// ============================================================================
// STATES
// ============================================================================
localparam [2:0] ST_IDLE = 3'd0,
ST_LOAD = 3'd1,
ST_BF_READ = 3'd2,
ST_BF_CALC = 3'd3,
ST_OUTPUT = 3'd4,
ST_DONE = 3'd5;
// Butterfly pipeline: READ → TW → MULT2 → SHIFT → WRITE (5 cycles)
// READ: Present BRAM addresses; register twiddle index (bf_tw_idx)
// TW: BRAM data valid → capture rd_a/rd_b; ROM lookup from registered
// twiddle index → capture rd_tw_cos/sin. This splits the combinational
// path (address calc + multiply + ROM + quarter-wave mux) into two cycles.
// MULT2: DSP multiply from registered data
// SHIFT: Arithmetic shift of DSP products
// WRITE: Add/subtract + BRAM writeback
localparam [3:0] ST_IDLE = 4'd0,
ST_LOAD = 4'd1,
ST_BF_READ = 4'd2,
ST_BF_TW = 4'd3,
ST_BF_MULT2 = 4'd4,
ST_BF_SHIFT = 4'd5,
ST_BF_WRITE = 4'd6,
ST_OUTPUT = 4'd7,
ST_DONE = 4'd8;
reg [2:0] state;
reg [3:0] state;
assign busy = (state != ST_IDLE);
// ============================================================================
@@ -114,10 +129,11 @@ reg [LOG2N:0] out_count;
reg [LOG2N-1:0] bfly_count;
reg [3:0] stage;
// Registered values (captured in BF_READ, used in BF_CALC)
// Registered values (captured in BF_READ, used in BF_TW and later)
reg signed [TWIDDLE_W-1:0] rd_tw_cos, rd_tw_sin;
reg [LOG2N-1:0] rd_addr_even, rd_addr_odd;
reg rd_inverse;
reg [LOG2N-1:0] rd_tw_idx; // registered twiddle index (breaks addr→ROM path)
// Half and twiddle stride
reg [LOG2N-1:0] half_reg;
@@ -155,7 +171,7 @@ always @(*) begin : tw_lookup
reg [LOG2N-1:0] k;
reg [LOG2N-1:0] rom_idx;
k = bf_tw_idx;
k = rd_tw_idx; // use registered index (set in ST_BF_READ)
tw_cos_lookup = 0;
tw_sin_lookup = 0;
@@ -197,24 +213,30 @@ function signed [DATA_W-1:0] saturate;
endfunction
// ============================================================================
// BUTTERFLY COMPUTATION (combinational, for BF_CALC write data)
// BUTTERFLY PIPELINE REGISTERS
// ============================================================================
reg signed [INTERNAL_W-1:0] bf_t_re, bf_t_im;
// Stage 1 (BF_MULT): Capture BRAM read data into rd_a, rd_b
// Stage 2 (BF_MULT2): DSP multiply + accumulate → raw products (bf_prod_re/im)
// Stage 3 (BF_WRITE): Shift (bit-select) + add/subtract + BRAM writeback
// ============================================================================
reg signed [INTERNAL_W-1:0] rd_a_re, rd_a_im; // registered BRAM port A data
reg signed [INTERNAL_W-1:0] rd_b_re, rd_b_im; // registered BRAM port B data (for twiddle multiply)
reg signed [INTERNAL_W-1:0] bf_t_re, bf_t_im; // twiddle products (after shift)
// Raw DSP products — full precision, registered to break DSP→CARRY4 path
// Width: 32*16 = 48 bits per multiply, sum of two = 49 bits max
localparam PROD_W = INTERNAL_W + TWIDDLE_W; // 48
reg signed [PROD_W:0] bf_prod_re, bf_prod_im; // 49 bits to hold sum of two products
// Combinational add/subtract from registered values (used in BF_WRITE)
reg signed [INTERNAL_W-1:0] bf_sum_re, bf_sum_im;
reg signed [INTERNAL_W-1:0] bf_dif_re, bf_dif_im;
always @(*) begin : bf_compute
if (!rd_inverse) begin
bf_t_re = (mem_rdata_b_re * rd_tw_cos + mem_rdata_b_im * rd_tw_sin) >>> (TWIDDLE_W - 1);
bf_t_im = (mem_rdata_b_im * rd_tw_cos - mem_rdata_b_re * rd_tw_sin) >>> (TWIDDLE_W - 1);
end else begin
bf_t_re = (mem_rdata_b_re * rd_tw_cos - mem_rdata_b_im * rd_tw_sin) >>> (TWIDDLE_W - 1);
bf_t_im = (mem_rdata_b_im * rd_tw_cos + mem_rdata_b_re * rd_tw_sin) >>> (TWIDDLE_W - 1);
end
bf_sum_re = mem_rdata_a_re + bf_t_re;
bf_sum_im = mem_rdata_a_im + bf_t_im;
bf_dif_re = mem_rdata_a_re - bf_t_re;
bf_dif_im = mem_rdata_a_im - bf_t_im;
always @(*) begin : bf_addsub
bf_sum_re = rd_a_re + bf_t_re;
bf_sum_im = rd_a_im + bf_t_im;
bf_dif_re = rd_a_re - bf_t_re;
bf_dif_im = rd_a_im - bf_t_im;
end
// ============================================================================
@@ -258,7 +280,19 @@ always @(*) begin : bram_port_mux
bram_addr_a = bf_addr_even;
bram_addr_b = bf_addr_odd;
end
ST_BF_CALC: begin
ST_BF_TW: begin
// BRAM outputs are being read; addresses were set in BF_READ
// Data is being captured into pipeline regs (rd_a, rd_b)
end
ST_BF_MULT2: begin
// Twiddle multiply from registered BRAM data (rd_b_re/im)
// No BRAM access needed this cycle
end
ST_BF_SHIFT: begin
// Shift (bit-select) from registered DSP products
// No BRAM access needed this cycle
end
ST_BF_WRITE: begin
bram_we_a = 1'b1;
bram_addr_a = rd_addr_even;
bram_wdata_a_re = bf_sum_re;
@@ -518,6 +552,15 @@ always @(posedge clk or negedge reset_n) begin
rd_addr_even <= 0;
rd_addr_odd <= 0;
rd_inverse <= 0;
rd_tw_idx <= 0;
rd_a_re <= 0;
rd_a_im <= 0;
rd_b_re <= 0;
rd_b_im <= 0;
bf_t_re <= 0;
bf_t_im <= 0;
bf_prod_re <= 0;
bf_prod_im <= 0;
end else begin
dout_valid <= 1'b0;
done <= 1'b0;
@@ -546,15 +589,58 @@ always @(posedge clk or negedge reset_n) begin
end
ST_BF_READ: begin
rd_tw_cos <= tw_cos_lookup;
rd_tw_sin <= tw_sin_lookup;
// Register butterfly addresses and twiddle index.
// BRAM read initiated by bram_port_mux (addresses presented
// combinationally); data arrives next cycle (ST_BF_TW).
// Twiddle ROM lookup uses rd_tw_idx next cycle, breaking the
// address-calc → ROM → quarter-wave-mux combinational path.
rd_addr_even <= bf_addr_even;
rd_addr_odd <= bf_addr_odd;
rd_inverse <= inverse;
state <= ST_BF_CALC;
rd_tw_idx <= bf_tw_idx;
state <= ST_BF_TW;
end
ST_BF_CALC: begin
ST_BF_TW: begin
// BRAM data valid this cycle (1-cycle read latency).
// Capture BRAM data into pipeline regs.
// Twiddle ROM lookup is combinational from registered rd_tw_idx
// — capture the result into rd_tw_cos/sin.
rd_a_re <= mem_rdata_a_re;
rd_a_im <= mem_rdata_a_im;
rd_b_re <= mem_rdata_b_re;
rd_b_im <= mem_rdata_b_im;
rd_tw_cos <= tw_cos_lookup;
rd_tw_sin <= tw_sin_lookup;
state <= ST_BF_MULT2;
end
ST_BF_MULT2: begin
// Compute raw twiddle products from registered BRAM data.
// Path: register → DSP48E1 multiply-accumulate → register (bf_prod_re/im)
// The shift is deferred to the next cycle to break the DSP→CARRY4 path.
if (!rd_inverse) begin
bf_prod_re <= rd_b_re * rd_tw_cos + rd_b_im * rd_tw_sin;
bf_prod_im <= rd_b_im * rd_tw_cos - rd_b_re * rd_tw_sin;
end else begin
bf_prod_re <= rd_b_re * rd_tw_cos - rd_b_im * rd_tw_sin;
bf_prod_im <= rd_b_im * rd_tw_cos + rd_b_re * rd_tw_sin;
end
state <= ST_BF_SHIFT;
end
ST_BF_SHIFT: begin
// Apply arithmetic right shift to registered DSP products.
// This is now register → bit-select/sign-extend → register,
// which should be near-zero logic (pure wiring + sign extension).
bf_t_re <= bf_prod_re >>> (TWIDDLE_W - 1);
bf_t_im <= bf_prod_im >>> (TWIDDLE_W - 1);
state <= ST_BF_WRITE;
end
ST_BF_WRITE: begin
// bf_sum/bf_dif are combinational from registered rd_a and bf_t.
// BRAM write data driven by bram_port_mux using bf_sum/bf_dif.
if (bfly_count == FFT_N_HALF_M1[LOG2N-1:0]) begin
bfly_count <= 0;
if (stage == LOG2N - 1) begin
9_Firmware/9_2_FPGA/fir_lowpass.v
+158 -60
View File
@@ -16,23 +16,57 @@ parameter COEFF_WIDTH = 18;
parameter DATA_WIDTH = 18;
parameter ACCUM_WIDTH = 36;
// Filter coefficients
// ============================================================================
// Pipelined FIR filter for 100 MHz timing closure
//
// Problem: The original fully-combinatorial adder tree for 32 multiply products
// created a 31-deep DSP48E1 PCOUT cascade chain taking 56.6ns (WNS = -48.325ns).
//
// Solution: 5-stage pipelined binary adder tree with registered outputs at
// each level. Each stage performs at most one pairwise addition (~1.7ns DSP hop),
// easily fitting in the 10ns clock period.
//
// Pipeline stages:
// Cycle 0: data_valid → shift delay line, start multiplies (combinatorial)
// Cycle 1: Register 32 multiply results + 16 pairwise sums (level 0)
// Cycle 2: 8 pairwise sums (level 1)
// Cycle 3: 4 pairwise sums (level 2)
// Cycle 4: 2 pairwise sums (level 3)
// Cycle 5: 1 final sum → accumulator_reg (level 4)
// Cycle 6: Output saturation/rounding (existing output stage)
//
// Total latency: 7 cycles from data_valid to data_out_valid
// Throughput: 1 sample per cycle (fully pipelined)
// FIR runs at 100 MHz on data decimated 4:1 from 400 MHz — valid samples
// arrive every ~4 cycles, so the 7-cycle latency is transparent.
// ============================================================================
// Filter coefficients (symmetric: coeff[k] == coeff[31-k])
reg signed [COEFF_WIDTH-1:0] coeff [0:TAPS-1];
// Parallel delay line
reg signed [DATA_WIDTH-1:0] delay_line [0:TAPS-1];
// Parallel multiply-accumulate structure
// Parallel multiply results (combinatorial)
wire signed [DATA_WIDTH+COEFF_WIDTH-1:0] mult_result [0:TAPS-1];
// Wires for parallel addition (combinatorial)
wire signed [ACCUM_WIDTH-1:0] sum_stage1_0, sum_stage1_1, sum_stage1_2, sum_stage1_3;
wire signed [ACCUM_WIDTH-1:0] sum_stage2_0, sum_stage2_1;
wire signed [ACCUM_WIDTH-1:0] sum_stage3;
// Registered accumulator
// Pipelined adder tree registers
// Level 0: 16 pairwise sums of 32 products
reg signed [ACCUM_WIDTH-1:0] add_l0 [0:15];
// Level 1: 8 pairwise sums
reg signed [ACCUM_WIDTH-1:0] add_l1 [0:7];
// Level 2: 4 pairwise sums
reg signed [ACCUM_WIDTH-1:0] add_l2 [0:3];
// Level 3: 2 pairwise sums
reg signed [ACCUM_WIDTH-1:0] add_l3 [0:1];
// Level 4: final sum
reg signed [ACCUM_WIDTH-1:0] accumulator_reg;
// Valid pipeline: 7-stage shift register
// [0]=multiply done, [1]=L0 done, [2]=L1 done, [3]=L2 done,
// [4]=L3 done, [5]=L4/accum done, [6]=output done
reg [6:0] valid_pipe;
// Initialize coefficients
initial begin
// Proper low-pass filter coefficients
@@ -46,7 +80,7 @@ initial begin
coeff[28] = 18'sh02A6; coeff[29] = 18'sh3FD87; coeff[30] = 18'sh00CE; coeff[31] = 18'sh00AD;
end
// Generate parallel multipliers
// Generate parallel multipliers (combinatorial — DSP48E1 will absorb these)
genvar k;
generate
for (k = 0; k < TAPS; k = k + 1) begin : mult_gen
@@ -54,71 +88,135 @@ generate
end
endgenerate
// COMBINATORIAL PARALLEL ADDITION TREE
// Stage 1: Group of 8
assign sum_stage1_0 = mult_result[0] + mult_result[1] + mult_result[2] + mult_result[3] +
mult_result[4] + mult_result[5] + mult_result[6] + mult_result[7];
assign sum_stage1_1 = mult_result[8] + mult_result[9] + mult_result[10] + mult_result[11] +
mult_result[12] + mult_result[13] + mult_result[14] + mult_result[15];
assign sum_stage1_2 = mult_result[16] + mult_result[17] + mult_result[18] + mult_result[19] +
mult_result[20] + mult_result[21] + mult_result[22] + mult_result[23];
assign sum_stage1_3 = mult_result[24] + mult_result[25] + mult_result[26] + mult_result[27] +
mult_result[28] + mult_result[29] + mult_result[30] + mult_result[31];
// Stage 2: Combine groups of 2
assign sum_stage2_0 = sum_stage1_0 + sum_stage1_1;
assign sum_stage2_1 = sum_stage1_2 + sum_stage1_3;
// Stage 3: Final sum
assign sum_stage3 = sum_stage2_0 + sum_stage2_1;
integer i;
// SINGLE-CYCLE PIPELINE PROCESSING
// ============================================================================
// Pipeline Stage 0: Shift delay line on data_valid
// ============================================================================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
// Reset delay line
for (i = 0; i < TAPS; i = i + 1) begin
delay_line[i] <= 0;
end
accumulator_reg <= 0;
data_out <= 0;
data_out_valid <= 0;
end else begin
// Always shift in new data when valid
if (data_valid) begin
// Shift delay line
for (i = TAPS-1; i > 0; i = i - 1) begin
delay_line[i] <= delay_line[i-1];
end
delay_line[0] <= data_in;
// Register the combinatorial sum
accumulator_reg <= sum_stage3;
// Output with 1-cycle latency
data_out_valid <= 1'b1;
end else begin
data_out_valid <= 1'b0;
end else if (data_valid) begin
for (i = TAPS-1; i > 0; i = i - 1) begin
delay_line[i] <= delay_line[i-1];
end
// Output saturation logic (registered)
if (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) begin
data_out <= (2**(DATA_WIDTH-1))-1;
end else if (accumulator_reg < -(2**(ACCUM_WIDTH-2))) begin
data_out <= -(2**(DATA_WIDTH-1));
end else begin
// Round and truncate (keep middle bits)
data_out <= accumulator_reg[ACCUM_WIDTH-2:DATA_WIDTH-1];
delay_line[0] <= data_in;
end
end
// ============================================================================
// Pipeline Stage 1 (Level 0): Register 16 pairwise sums of 32 multiply results
// Each addition is a single 36-bit add — one DSP48E1 hop (~1.7ns), fits 10ns.
// ============================================================================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
for (i = 0; i < 16; i = i + 1) begin
add_l0[i] <= 0;
end
end else if (valid_pipe[0]) begin
for (i = 0; i < 16; i = i + 1) begin
add_l0[i] <= {{(ACCUM_WIDTH-DATA_WIDTH-COEFF_WIDTH){mult_result[2*i][DATA_WIDTH+COEFF_WIDTH-1]}}, mult_result[2*i]} +
{{(ACCUM_WIDTH-DATA_WIDTH-COEFF_WIDTH){mult_result[2*i+1][DATA_WIDTH+COEFF_WIDTH-1]}}, mult_result[2*i+1]};
end
end
end
// Always ready to accept new data
// ============================================================================
// Pipeline Stage 2 (Level 1): 8 pairwise sums of 16 Level-0 results
// ============================================================================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
for (i = 0; i < 8; i = i + 1) begin
add_l1[i] <= 0;
end
end else if (valid_pipe[1]) begin
for (i = 0; i < 8; i = i + 1) begin
add_l1[i] <= add_l0[2*i] + add_l0[2*i+1];
end
end
end
// ============================================================================
// Pipeline Stage 3 (Level 2): 4 pairwise sums of 8 Level-1 results
// ============================================================================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
for (i = 0; i < 4; i = i + 1) begin
add_l2[i] <= 0;
end
end else if (valid_pipe[2]) begin
for (i = 0; i < 4; i = i + 1) begin
add_l2[i] <= add_l1[2*i] + add_l1[2*i+1];
end
end
end
// ============================================================================
// Pipeline Stage 4 (Level 3): 2 pairwise sums of 4 Level-2 results
// ============================================================================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
add_l3[0] <= 0;
add_l3[1] <= 0;
end else if (valid_pipe[3]) begin
add_l3[0] <= add_l2[0] + add_l2[1];
add_l3[1] <= add_l2[2] + add_l2[3];
end
end
// ============================================================================
// Pipeline Stage 5 (Level 4): Final sum of 2 Level-3 results
// ============================================================================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
accumulator_reg <= 0;
end else if (valid_pipe[4]) begin
accumulator_reg <= add_l3[0] + add_l3[1];
end
end
// ============================================================================
// Pipeline Stage 6: Output saturation/rounding (registered)
// ============================================================================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
data_out <= 0;
data_out_valid <= 0;
end else begin
data_out_valid <= valid_pipe[5];
if (valid_pipe[5]) begin
// Output saturation logic
if (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) begin
data_out <= (2**(DATA_WIDTH-1))-1;
end else if (accumulator_reg < -(2**(ACCUM_WIDTH-2))) begin
data_out <= -(2**(DATA_WIDTH-1));
end else begin
// Round and truncate (keep middle bits)
data_out <= accumulator_reg[ACCUM_WIDTH-2:DATA_WIDTH-1];
end
end
end
end
// ============================================================================
// Valid pipeline shift register
// ============================================================================
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
valid_pipe <= 7'b0000000;
end else begin
valid_pipe <= {valid_pipe[5:0], data_valid};
end
end
// Always ready to accept new data (fully pipelined)
assign fir_ready = 1'b1;
// Overflow detection (simplified)
// Overflow detection
assign filter_overflow = (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) ||
(accumulator_reg < -(2**(ACCUM_WIDTH-2)));
endmodule
endmodule
9_Firmware/9_2_FPGA/nco_400m_enhanced.v
+94 -44
View File
@@ -12,43 +12,62 @@ module nco_400m_enhanced (
);
// ============================================================================
// 4-stage pipelined NCO for 400 MHz timing closure
// 6-stage pipelined NCO for 400 MHz timing closure
//
// Stage 1: Phase accumulator update (DSP48E1 in P=P+C mode) + offset addition
// Stage 1: Phase accumulator update (DSP48E1 in P=P+C mode)
// DSP48E1 does: P_reg <= P_reg + C_port (frequency_tuning_word)
// The P register output IS the phase accumulator — no CARRY4 chain.
// phase_with_offset = P_output + {phase_offset, 16'b0} (registered)
// Stage 2: LUT address decode + LUT read → register abs values + quadrant
// Stage 3: Compute negations from registered abs values → register neg values
// phase_accum_reg <= P_output[31:0] (fabric register captures DSP output)
// Stage 2: Offset addition in fabric (registered)
// phase_with_offset <= phase_accum_reg + {phase_offset, 16'b0}
// Breaking DSP→CARRY4 into two registered stages eliminates the
// critical path (was -0.594ns WNS in Build 6)
// Stage 3a: Register LUT address (lut_index) and quadrant from phase_with_offset
// Only 2 registers driven (minimal fanout, short routes)
// Stage 3b: LUT read using registered lut_index → register abs values + quadrant
// Registered LUT address → combinational LUT6 read → register
// Eliminates the routing-dominant critical path (-0.100ns in Build 8)
// Stage 4: Compute negations from registered abs values → register neg values
// (CARRY4 x4 chain has registered inputs, fits in 2.5ns easily)
// Stage 4: Quadrant sign application → sin_out, cos_out (pure MUX, no arith)
// Stage 5: Quadrant sign application → sin_out, cos_out (pure MUX, no arith)
//
// Total latency: 4 cycles from phase_valid to sin/cos output
// Max logic levels per stage: Stage 1=DSP48E1(internal), Stage 2=2(LUT3+LUT6),
// Stage 3=4(CARRY4 chain), Stage 4=1(MUX)
// Total latency: 6 cycles from phase_valid to sin/cos output
// Max logic levels per stage: Stage 1=DSP48E1(internal), Stage 2=4(CARRY4x5),
// Stage 3a=1(LUT3 quadrant+index decode), Stage 3b=1(LUT6 ROM read),
// Stage 4=4(CARRY4 chain), Stage 5=1(MUX)
// ============================================================================
// Phase accumulator — DSP48E1 P output provides the accumulated phase
// In simulation: behavioral reg. In synthesis: DSP48E1 P[31:0].
reg [31:0] phase_with_offset;
reg [31:0] phase_accum_reg; // Stage 1 output: registered DSP48E1 P[31:0]
reg [31:0] phase_with_offset; // Stage 2 output: phase_accum_reg + offset
// Stage 2 pipeline registers: LUT output + quadrant
// Stage 3a pipeline registers: registered LUT address + quadrant
reg [5:0] lut_index_pipe;
reg [1:0] quadrant_pipe;
// Stage 3b pipeline registers: LUT output + quadrant
reg [15:0] sin_abs_reg, cos_abs_reg;
reg [1:0] quadrant_reg;
// Stage 3 pipeline registers: pre-computed negations + abs copies + quadrant
// Stage 4 pipeline registers: pre-computed negations + abs copies + quadrant
reg signed [15:0] sin_neg_reg, cos_neg_reg;
reg [15:0] sin_abs_reg2, cos_abs_reg2; // Pass-through for Stage 4 MUX
reg [1:0] quadrant_reg2; // Pass-through for Stage 4 MUX
reg [15:0] sin_abs_reg2, cos_abs_reg2; // Pass-through for Stage 5 MUX
reg [1:0] quadrant_reg2; // Pass-through for Stage 5 MUX
// Valid pipeline: tracks 4-stage latency
reg [3:0] valid_pipe;
// Valid pipeline: tracks 6-stage latency
reg [5:0] valid_pipe;
// Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
wire [7:0] lut_address = phase_with_offset[31:24];
// Quarter-wave sine LUT (0-90 degrees only)
reg [15:0] sin_lut [0:63]; // 64 entries for 0-90 degrees
// Force distributed RAM (LUTRAM) — the 64x16 LUT is only 1024 bits, far too
// small for BRAM. BRAM CLK→DOADO delay (2.454ns) + downstream negation logic
// (1.236ns) exceeded the 2.5ns period at 400 MHz (WNS = -2.238ns). LUTRAM
// read is combinatorial (~0.5ns through LUTs), giving the Stage 2→3 negation
// path ~2.1ns of budget which fits comfortably.
(* ram_style = "distributed" *) reg [15:0] sin_lut [0:63]; // 64 entries for 0-90 degrees
// Initialize sine LUT
integer lut_init_i;
@@ -78,16 +97,20 @@ initial begin
sin_lut[60] = 16'h7F61; sin_lut[61] = 16'h7FA6; sin_lut[62] = 16'h7FD8; sin_lut[63] = 16'h7FF5;
end
// Combinational: quadrant determination and LUT index (feeds Stage 2 registers)
// Combinational: quadrant determination and LUT index (feeds Stage 3a registers)
wire [1:0] quadrant_w = lut_address[7:6];
wire [5:0] lut_index = (quadrant_w[0] ^ quadrant_w[1]) ? ~lut_address[5:0] : lut_address[5:0];
// Combinational LUT read (will be registered in Stage 2)
wire [15:0] sin_abs_w = sin_lut[lut_index];
wire [15:0] cos_abs_w = sin_lut[63 - lut_index];
// Combinational LUT read using REGISTERED lut_index_pipe (feeds Stage 3b registers)
// These wires are driven by lut_index_pipe (registered in Stage 3a), so the
// combinational path is just: lut_index_pipe_reg → LUT6 (distributed RAM read)
// This eliminates the LUT3→LUT6 two-level critical path from Build 8.
wire [15:0] sin_abs_w = sin_lut[lut_index_pipe];
wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe];
// ============================================================================
// Stage 1: Phase accumulator (DSP48E1) + offset addition (fabric register)
// Stage 1: Phase accumulator (DSP48E1) — accumulates FTW each cycle
// Stage 2: Offset addition in fabric — breaks DSP→CARRY4 critical path
//
// The phase accumulator is the critical path bottleneck: a 32-bit addition
// requires 8 CARRY4 stages in fabric (2.826 ns > 2.5 ns budget at 400 MHz).
@@ -98,23 +121,30 @@ wire [15:0] cos_abs_w = sin_lut[63 - lut_index];
// - The DSP48E1 48-bit ALU performs the add internally at full speed
// - Only P[31:0] is used (32-bit phase accumulator)
//
// phase_with_offset is computed in fabric: DSP48E1 P output + {phase_offset, 16'b0}
// This is OK because both operands are registered (P is PREG output, phase_offset
// is a stable input), and the result feeds Stage 2 LUT which is also registered.
// Phase offset addition is split into a separate pipeline stage:
// Stage 1: phase_accum_reg <= P[31:0] (just capture the DSP output)
// Stage 2: phase_with_offset <= phase_accum_reg + {phase_offset, 16'b0}
// This eliminates the DSP48E1.P→CARRY4 chain critical path (-0.594ns in Build 6).
// ============================================================================
`ifdef SIMULATION
// ---- Behavioral model for Icarus Verilog simulation ----
// Mimics DSP48E1 accumulator: P <= P + C, with CREG=1, PREG=1
// Stage 1: phase_accum_reg captures accumulator output
// Stage 2: phase_with_offset adds phase offset
reg [31:0] phase_accumulator;
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
phase_accumulator <= 32'h00000000;
phase_accum_reg <= 32'h00000000;
phase_with_offset <= 32'h00000000;
end else if (phase_valid) begin
// Stage 1: accumulate + capture
phase_accumulator <= phase_accumulator + frequency_tuning_word;
phase_with_offset <= phase_accumulator + {phase_offset, 16'b0};
phase_accum_reg <= phase_accumulator;
// Stage 2: offset addition (uses previous cycle's phase_accum_reg)
phase_with_offset <= phase_accum_reg + {phase_offset, 16'b0};
end
end
@@ -211,39 +241,59 @@ DSP48E1 #(
.PCOUT()
);
// phase_with_offset: add phase_offset to the DSP48E1 accumulator output
// Both operands are registered (phase_accum_p from PREG, phase_offset is stable input)
// This fabric add feeds Stage 2 LUT which is also registered — timing is fine
// Stage 1: Capture DSP48E1 P output into fabric register
// Stage 2: Add phase offset to captured value
// Split into two registered stages to break DSP48E1.P→CARRY4 critical path
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
phase_accum_reg <= 32'h00000000;
phase_with_offset <= 32'h00000000;
end else if (phase_valid) begin
phase_with_offset <= phase_accum_p[31:0] + {phase_offset, 16'b0};
// Stage 1: just capture DSP output (no CARRY4 chain)
phase_accum_reg <= phase_accum_p[31:0];
// Stage 2: offset add (CARRY4 chain from registered fabric→fabric, easy timing)
phase_with_offset <= phase_accum_reg + {phase_offset, 16'b0};
end
end
`endif
// ============================================================================
// Stage 2: LUT read + register absolute values and quadrant
// Only LUT decode here — negation is deferred to Stage 3
// Stage 3a: Register LUT address and quadrant from phase_with_offset
// Only 2 registers driven (lut_index_pipe + quadrant_pipe)
// Minimal fanout → short routes → easy timing
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
lut_index_pipe <= 6'b000000;
quadrant_pipe <= 2'b00;
end else if (valid_pipe[1]) begin
lut_index_pipe <= lut_index;
quadrant_pipe <= quadrant_w;
end
end
// ============================================================================
// Stage 3b: LUT read using registered lut_index_pipe + register abs values
// Registered address → combinational LUT6 read → register
// Only 1 logic level (LUT6), trivial timing
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
sin_abs_reg <= 16'h0000;
cos_abs_reg <= 16'h7FFF;
quadrant_reg <= 2'b00;
end else if (valid_pipe[0]) begin
end else if (valid_pipe[2]) begin
sin_abs_reg <= sin_abs_w;
cos_abs_reg <= cos_abs_w;
quadrant_reg <= quadrant_w;
quadrant_reg <= quadrant_pipe;
end
end
// ============================================================================
// Stage 3: Compute negations from registered abs values
// Stage 4: Compute negations from registered abs values
// CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
// Also pass through abs values and quadrant for Stage 4
// Also pass through abs values and quadrant for Stage 5
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
@@ -252,7 +302,7 @@ always @(posedge clk_400m or negedge reset_n) begin
sin_abs_reg2 <= 16'h0000;
cos_abs_reg2 <= 16'h7FFF;
quadrant_reg2 <= 2'b00;
end else if (valid_pipe[1]) begin
end else if (valid_pipe[3]) begin
sin_neg_reg <= -sin_abs_reg;
cos_neg_reg <= -cos_abs_reg;
sin_abs_reg2 <= sin_abs_reg;
@@ -262,14 +312,14 @@ always @(posedge clk_400m or negedge reset_n) begin
end
// ============================================================================
// Stage 4: Quadrant sign application → final sin/cos output
// Uses pre-computed negated values from Stage 3 — pure MUX, no arithmetic
// Stage 5: Quadrant sign application → final sin/cos output
// Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
sin_out <= 16'h0000;
cos_out <= 16'h7FFF;
end else if (valid_pipe[2]) begin
end else if (valid_pipe[4]) begin
case (quadrant_reg2)
2'b00: begin // Quadrant I: sin+, cos+
sin_out <= sin_abs_reg2;
@@ -292,15 +342,15 @@ always @(posedge clk_400m or negedge reset_n) begin
end
// ============================================================================
// Valid pipeline and dds_ready (4-stage latency)
// Valid pipeline and dds_ready (6-stage latency)
// ============================================================================
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
valid_pipe <= 4'b0000;
valid_pipe <= 6'b000000;
dds_ready <= 1'b0;
end else begin
valid_pipe <= {valid_pipe[2:0], phase_valid};
dds_ready <= valid_pipe[3];
valid_pipe <= {valid_pipe[4:0], phase_valid};
dds_ready <= valid_pipe[5];
end
end
9_Firmware/9_2_FPGA/tb/tb_nco_400m.v
+6 -6
View File
@@ -259,16 +259,16 @@ module tb_nco_400m;
#1;
sin_before_gate = sin_out;
// Deassert phase_valid — with 4-stage pipeline, dds_ready has 5-cycle latency
// Deassert phase_valid — with 6-stage pipeline, dds_ready has 7-cycle latency
phase_valid = 0;
repeat (6) @(posedge clk_400m); #1;
repeat (8) @(posedge clk_400m); #1;
check(dds_ready === 1'b0, "dds_ready deasserts when phase_valid=0");
repeat (10) @(posedge clk_400m);
// Re-enable — wait for pipeline to refill (5 cycles)
// Re-enable — wait for pipeline to refill (7 cycles)
phase_valid = 1;
repeat (6) @(posedge clk_400m); #1;
repeat (8) @(posedge clk_400m); #1;
check(dds_ready === 1'b1, "dds_ready re-asserts when phase_valid=1");
// ════════════════════════════════════════════════════════
@@ -285,8 +285,8 @@ module tb_nco_400m;
frequency_tuning_word = FTW_10MHZ;
phase_valid = 1;
// Skip pipeline warmup (4-stage pipeline + 1 for dds_ready)
repeat (5) @(posedge clk_400m);
// Skip pipeline warmup (6-stage pipeline + 1 for dds_ready)
repeat (7) @(posedge clk_400m);
mag_sq_min = 32'hFFFFFFFF;
mag_sq_max = 32'h00000000;