From 0009a74a492616b07f347b5a87714a15718c3db8 Mon Sep 17 00:00:00 2001 From: Jason <83615043+JJassonn69@users.noreply.github.com> Date: Thu, 19 Mar 2026 14:57:56 +0200 Subject: [PATCH] Expand pre-hardware bring-up readiness docs --- docs/bring-up.html | 119 ++++++++++++++++++++++++++++++++++++--------- docs/index.html | 38 +++++++-------- 2 files changed, 116 insertions(+), 41 deletions(-) diff --git a/docs/bring-up.html b/docs/bring-up.html index b517138..2104937 100644 --- a/docs/bring-up.html +++ b/docs/bring-up.html @@ -24,29 +24,28 @@

Execution Checklist

Hardware Bring-Up Plan

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Operational sequence and pass/fail gates for Day-1 and post-Day-1 validation.

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Pre-arrival completeness gates, board-day smoke tests, and fault-localization rules for the first FPGA module and carrier-board sessions.

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Bring-up gates

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Pre-arrival completeness gates

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StepGate Objective Pass CriteriaEvidence
1Program baseline bitstreamJTAG detect + successful configuration
2Clock/reset sanityStable clocks and deterministic reset release
3ADC front-endValid raw data visible in ILA on expected clock
4DDC verificationExpected valid strobe and non-zero I/Q outputs
5Matched filter stageRange profile valid asserted and segment flow correct
6Range/Doppler pipelineDeterministic frame outputs with full bin coverage
7USB host linkSustained transfer and stable framing over soak window
8Thermal/power screenNo rail anomalies or thermal runaway under load
1Freeze known-good firmware and bitstream baselinesTracked commit, named artifact set, and repeatable programming flow are availableGit commit, bitstream path, reports, programming TCL
2Preserve clean implementation constraintsPositive WNS/WHS/WPWS, XDCB-5 cleared, only documented methodology residue remainsTiming summary and methodology report
3Keep regressions green before board arrivalMCU host tests and FPGA regression/integration suites pass on the tracked tree15/15 MCU and 18/18 FPGA logs
4Make first-power-on behavior observableClock, LO, beamformer, PA, and USB status can be identified from logs or status outputsDIAG coverage, status fields, ILA/debug plan
5Prepare board-arrival execution checklistPower order, abort criteria, and host-side capture steps are written and reviewedThis page plus reports and scripts references
6Document unresolved pre-hardware risksOpen issues are explicitly listed so Day-0 findings are interpreted correctlyKnown-open-risks section below
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Day-1 quick sequence

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Board-arrival smoke test

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  1. Mount SoM on carrier and verify supply/jumper defaults.
    2. -
  2. Program minimal heartbeat top for immediate hardware liveness check.
    3. -
  3. Program debug bitstream and attach LTX for ILA sessions.
    4. -
  4. Capture first ADC and DDC traces, compare with expected signatures.
    5. +
  5. Inspect carrier defaults, regulator enables, jumpers, and any board-level clock source selections before power is applied.
    6. +
  6. Power the carrier and module in the safest configuration with RF transmit paths disabled and document current draw immediately.
    7. +
  7. Run the FPGA programming flow, verify JTAG enumeration, and confirm DONE and INIT_COMPLETE from the hardware manager script.
    8. +
  8. Check deterministic reset release and heartbeat/status outputs before enabling any analog or RF-dependent function.
    9. +
  9. Bring up MCU firmware logging, confirm AD9523 status pins, LO initialization results, and beamformer communication readback.
    10. +
  10. Use the debug-capable FPGA image and probes to confirm raw ADC, DDC, matched-filter, and USB-path activity in that order.
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  11. Exercise the FT601 path with known framing expectations before any long-duration streaming test.
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  12. Only after all previous steps pass, begin PA bias, calibration, and higher-risk RF activation.
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Risk controls

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Abort criteria

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  • Keep production target untouched; use split dev targets for carrier-specific pinouts.
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  • Do not rely on RTL hierarchical net names in post-synth debug scripts.
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  • Run timing/CDC/exceptions checks after every target migration update.
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  • Use a repeatable program-capture checklist to detect intermittent reset/clock issues.
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  • Stop immediately on unexpected rail current, regulator instability, or thermal rise beyond the planned idle envelope.
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  • Do not continue past LO bring-up if the lock GPIOs or lock-status reads disagree repeatedly.
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  • Stop RF activation if beamformer scratchpad/readback checks fail on any device.
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  • Do not continue USB stress testing if framing, backpressure, or bus-direction behavior is inconsistent.
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  • Revert to the heartbeat or debug image if reset sequencing or clock presence is ambiguous.
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  • Keep the production-target constraints and pinout source untouched while bring-up-specific targets are being adjusted.
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First-power-on observability targets

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SubsystemWhat must be visibleExpected evidence
FPGA configurationJTAG enumeration, DONE, INIT_COMPLETE, optional ILA probe presenceprogram_fpga.tcl summary and hardware-manager status
ClockingAD9523 status pins and deterministic downstream reset releaseDIAG clock messages and status GPIO snapshots
LO chainADF4382A init status, timed-sync path status, TX/RX lock stateUSART3 DIAG log plus lock GPIO behavior
Beamformer controlPer-device communication sanity and basic temperature readbackADAR1000 scratchpad/readback and temperature prints
PA biasingDAC/ADC bring-up progression and IDQ calibration convergence boundsPer-channel PA DIAG output with stop conditions
FPGA data pathADC, DDC, matched-filter, and USB-path activity in sequenceILA captures and system status outputs
USB/FT601 linkStable framing, no obvious underrun/backpressure surprises, host decode sanityHost capture script output and stable packet boundaries
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Required artifacts before hardware arrives

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  • Named firmware baseline commit and build instructions for the MCU image.
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  • Named FPGA baseline bitstream and matching `.ltx` probes file for debug sessions.
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  • Current production-target XDC, timing summary, and methodology report.
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  • Programming and debug TCL scripts for baseline and debug images.
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  • Regression evidence for the tracked branch: MCU host suite and FPGA regression/integration suite.
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  • Day-0 measurement sheet covering supply currents, temperatures, and observed status outputs.
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Host-side tools and workflows

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  • JTAG programming workflow using the checked-in Vivado TCL scripts.
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  • Serial capture on USART3 with timestamps preserved for bring-up logs.
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  • FT601 or host-side USB capture/decoder workflow to validate framing and payload stability.
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  • ILA capture workflow for raw ADC, DDC, matched-filter, and USB-domain checkpoints.
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  • Repeatable checklist for baseline image, debug image, and rollback image selection.
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Known open risks before board arrival

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RiskCurrent stateDay-0 handling
Residual FT601 methodology warningProduction-target XDC cleanup is validated, but one `ft601_txe` methodology residue remains documented.Treat as a known observation item and verify real FT601 status behavior before attempting deeper constraint churn.
RF control-path realismFirmware sequencing and diagnostics improved, but LO sync, phase behavior, and beamformer control still require physical validation.Use readback-first bring-up and do not assume analog behavior from simulation or logs alone.
Prototype-grade top-level functional assumptionsThe active FPGA baseline is regression-clean, but some radar-function behavior still needs real-board confirmation under actual I/O conditions.Validate each data-path stage incrementally with ILA and host captures before full streaming claims.
PA calibration boundariesIDQ calibration logic is much safer than before, but real-device convergence and margin limits are not yet board-proven.Use conservative limits, observe every channel, and stop on abnormal current or non-convergent channels.
Board-specific integration unknownsCarrier/module interaction, rails, clocks, and connector assumptions remain partially unproven until first assembly.Begin with lowest-risk heartbeat and configuration checks before enabling higher-energy subsystems.
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diff --git a/docs/index.html b/docs/index.html index 4e13ef1..e50b442 100644 --- a/docs/index.html +++ b/docs/index.html @@ -24,33 +24,33 @@

Open-Source Phased Array Radar

Engineering Documentation Site

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This site tracks architecture, FPGA improvements, timing closure outcomes, and hardware bring-up readiness for AERIS-10.

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This site tracks architecture, validated implementation baselines, constraint cleanup progress, and pre-hardware bring-up readiness for AERIS-10.

View Change Timeline - Open Bring-Up Checklist + Open Readiness Package
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Build 13 Timing

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WNS +0.311 ns

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TNS 0.000, WHS +0.060, THS 0.000

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Tracked Timing Baseline

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WNS +0.058 ns

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WHS +0.068, WPWS +0.684 after validated Build 16 XDC port

Regression Status

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13 / 13 Suites

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Integration golden match: 2048 / 2048

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MCU 15 / 15, FPGA 18 / 18

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Host firmware regression plus FPGA unit and integration suites passing

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Debug Instrumentation

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4 ILA Cores

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92 probe bits, 4096 depth

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Methodology State

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XDCB-5 = 0

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Single documented TIMING-18 residue on `ft601_txe` async observation

Current Phase

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Hardware Bring-Up

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TE0712/TE0713 split targets prepared

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Pre-Hardware Readiness

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Board-arrival smoke test, artifact inventory, and open-risk tracking prepared

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What changed recently

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